Title:
Implementing Legacy-C Algorithms in FPGA Co-Processors for Performance Accelerated Smart Payloads
Implementing Legacy-C Algorithms in FPGA Co-Processors for Performance Accelerated Smart Payloads
Author(s)
Pingree, Paula J.
Scharenbroich, Lucas J.
Werne, Thomas A.
Hartzell, Christine
Scharenbroich, Lucas J.
Werne, Thomas A.
Hartzell, Christine
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Abstract
Accurate, on-board classification of instrument
data is used to increase science return by autonomously
identifying regions of interest for priority transmission or
generating summary products to conserve transmission
bandwidth. Due to on-board processing constraints, such
classification has been limited to using the simplest
functions on a small subset of the full instrument data.
FPGA co-processor designs for SVM classifiers will lead
to significant improvement in on-board classification
capability and accuracy.
We implemented a SWIL classifier, developed for the
Hyperion instrument on the EO-1 spacecraft, on the Xilinx
Virtex-4FX60 FPGA as a baseline challenge. We have taken
advantage of Impulse, the commercially available C-to-
HDL tool by Impulse Accelerated Technologies, which
supports the development of highly parallel, co-designed
hardware algorithms (from software) and applications. This
paper describes our approach for implementing the
Hyperion linear SVM on the Virtex-4FX FPGA, as well as
additional experiments with increased numbers of data
bands and a more sophisticated SVM kernel to show the
potential for better on-board classification achieved with board
embedded FPGAs over current in-flight capabilities.
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Date Issued
2008-03
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Text
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Paper
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