Title:
Frequency dividers design for multi-GHz PLL systems
Frequency dividers design for multi-GHz PLL systems
Author(s)
Barale, Francesco
Advisor(s)
Laskar, Joy
Editor(s)
Collections
Supplementary to
Permanent Link
Abstract
In this work, a programmable frequency divider suitable for millimeter wave
phase-lock loops is presented. The frequency divider has been implemented in a
90 nm standard CMOS technology. To the extent of maximizing the operative input
frequency, the higher frequency digital blocks of the frequency divider have been
realized using dynamic precharge-evaluation logic. Moreover, a non-conventional
method to implement non-power-of-2 division ratios has been used for the higher
frequency divider stages (input stages).
Sponsor
Date Issued
2008-06-16
Extent
Resource Type
Text
Resource Subtype
Thesis