Experimentally validated multiscale thermal modeling of electronic cabinets

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Nie, Qihong
Joshi, Yogendra
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Thermal characterization of electronic cabinets is becoming increasingly important, due to growing power dissipation and compact packaging. Usually, multiple length scales of interest and modes of heat transfer are simultaneously present. A steady reduced order thermal modeling framework for electronic cabinets was developed to provide an efficient method to model thermal transport across multiple length scales. This methodology takes advantage of compact modeling at the chip or component level and reduced order modeling at subsystem and cabinet levels. Compact models, which were incorporated into system level simulation, were created for components, and reduced order models (ROMs) were developed using proper orthogonal decomposition (POD) for subsystems and system. An efficient interfacial coupling scheme was developed using the concept of flow network modeling to couple the heat and mass flow rates and pressure at each interface, when interconnecting ROMs together to simulate the entire system. Thermal information was then subsequently extracted from the global modeling and applied to the component model for detailed simulation. A boundary profile-matching scheme for ROM of each subsystem was developed to broaden the applicability of the multi-scale thermal modeling methodology. The output profiles of the subsystem upstream can be transferred to the input profiles of the subsystems downstream by adding necessary flow straightening ducts during the snapshots generation process. A general method to create dynamic multi-layer compact models for components and modules was developed. These dynamic compact models were incorporated into enclosure level simulation. The dynamic reduced order model for the enclosure was developed using POD. The transient multi-scale thermal modeling approach was illustrated through an electronic enclosure with insulated gate bipolar transistor (IGBT) module. The multiscale thermal modeling methodology presented here was validated through experiments conducted on a simulated electronic cabinet and the test vehicle with hybrid cooling technique. The latter incorporated double-sided cooling with hybrid forced air convection, thermoelectric cooling, and micro-channel liquid cooling. The overall multi-scale modeling framework was able to reduced numerical models containing 107 DOF down to around 102, while still retaining an approximation accuracy of around 90% in prediction of chip junction temperature rises, compared to measurements.
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