Title:
Designing High-Performance Microprocessors in 3-Dimensional Integration Technology

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dc.contributor.advisor Loh, Gabriel H.
dc.contributor.advisor Lee, Hsien-Hsin Sean
dc.contributor.author Puttaswamy, Kiran en_US
dc.contributor.committeeMember Lim, Sung Kyu
dc.contributor.committeeMember Prvulovic, Milos
dc.contributor.committeeMember Yalamanchili, Sudhakar
dc.contributor.committeeMember Yoder, Douglas
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2008-02-07T18:17:14Z
dc.date.available 2008-02-07T18:17:14Z
dc.date.issued 2007-11-08 en_US
dc.description.abstract The main contribution of this dissertation is the demonstration of the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, thus reducing delay, power consumption, and area. To adapt planar microarchitectures to 3D-integrated designs, we study several building blocks that together comprise a substantial portion of a processor s total transistor count. In particular, we focus our attention on three basic circuit classes: static random access memory (SRAM) circuits, associative/CAM logic circuits, and data processing in conventional high-performance processors. We propose 2-die-stacked and 4-die-stacked 3D-integrated circuits to deal with the constraints of the conventional planar technology. We propose high-performance 3D-integrated microprocessors and evaluate the impact on performance, power, and temperature. We demonstrate two different approaches to improve performance: clock speed (3D-integrated processors with identical microarchitectural configurations as the corresponding planar processor run at a higher clock frequency), and IPC (3D-integrated processors accommodate larger-sized modules than the planar processors for the same frequency). We demonstrate the simultaneous benefits of the 3D-integration and highlight the power density and thermal issues related to the 3D-integration technology. Next, we propose microarchitectural techniques based on significance partitioning and data-width locality to effectively address the challenges of power density and temperature. We demonstrate that our microarchitecture-level techniques can effectively control the power density issues in the 3D-integrated processors. The 3D-integrated processors provide a significant performance benefit over the planar processors while simultaneously reducing the total power. The simultaneous benefits in multiple objectives make 3D-integration a highly desirable technology for use in building future microprocessors. One of the key contributions of this dissertation is the temperature analysis that shows that the worst-case temperatures on the 3D-integrated processors can be effectively controlled using microarchitecture level techniques. The 3D-integration technology may extend the applicability of Moore s law for a few more technology generations. en_US
dc.description.degree Ph.D. en_US
dc.identifier.uri http://hdl.handle.net/1853/19759
dc.publisher Georgia Institute of Technology en_US
dc.subject High-performance microprocessors en_US
dc.subject 3D integration technology en_US
dc.subject.lcsh Integrated circuits Large scale integration
dc.subject.lcsh Temperature control
dc.subject.lcsh High performance processors
dc.title Designing High-Performance Microprocessors in 3-Dimensional Integration Technology en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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