Title:
Design and Reliability of mm-Wave Circuits In Silicon-Germanium
Design and Reliability of mm-Wave Circuits In Silicon-Germanium
Author(s)
Moradinia, Arya
Advisor(s)
Cressler, John D.
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Abstract
The first goal of this research is to develop a methodology for the design of RF and
mm-Wave circuits in Silicon-Germanium utilizing CMOS, PIN diodes, and passive
circuits. Such circuits consist of a 2-20 GHz CMOS-based TR (Transmit/Receive) SPDT
switch and an 18-47 GHz Wilkinson Power Divider-Combiner (WPDC). Optimal design
techniques are utilized in these circuit designs to overcome the limitations of both Front
End of the Line (FEOL: active devices) and Back End of the Line (BEOL: metal stack-up)
in a commercial SiGe BiCMOS processes. The resulting performances utilize novel design
techniques that allow them to be competitive with existing state-of-the-art designs across
multiple IC technologies.
The second goal of this research is to understand the impact of DC reliability
mechanisms on AC performance for analog SiGe HBT circuits and to locate an optimal
DC biasing regime that balances the tradeoff between circuit reliability and performance.
The circuit of interest is a DC-100 GHz wireline driver, which is widely used as a critical
block in optical communications. The aim is to extend the concept of Safe Operating Area
(SOA), which is the region of the DC I-V plane that does not damage a device over time,
to the circuit level. This is done with the introduction of a performance-informed Circuit Safe Operating Area (C-SOA), which is defined as the region of the DC I-V plane that does
not result in a degradation to AC performance over time while maintaining the best possible
AC performance. The wireline driver’s highlighted AC performance is the OP1dB or output referred 1-dB compression point.
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Date Issued
2021-05-04
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