Title:
Process modeling and optimization using industrial semiconductor fabrication data

dc.contributor.advisor May, Gary S.
dc.contributor.author Mevawalla, Zubin
dc.contributor.committeeMember Frazier, Albert B.
dc.contributor.committeeMember Milor, Linda S.
dc.contributor.committeeMember Bakir, Muhannad S.
dc.contributor.committeeMember Kohl, Paul A.
dc.contributor.department Electrical and Computer Engineering
dc.date.accessioned 2015-06-08T18:02:14Z
dc.date.available 2015-06-08T18:02:14Z
dc.date.created 2015-05
dc.date.issued 2015-01-05
dc.date.submitted May 2015
dc.date.updated 2015-06-08T18:02:14Z
dc.description.abstract Manufacturers address the distinct operational objectives of product innovation and manufacturing efficiency by having separate fabrication facilities (“fabs”) for development and manufacturing. Additionally, the industrial manufacture of a semiconductor product proceeds through several stages of production. These are typically a research and development (R&D) stage, a ramping stage, and a manufacturing stage. These production stages are distributed over the different fabs. These differences in fabrication environment and stage of production result in differences in the characteristics of production of a semiconductor product over its manufacturing lifetime. Some examples of these differences are device yield, breadth of processing conditions, throughput, number of reaction chambers operating in parallel, metrology, and data collection. These differences are reflected in the data available in the fab databases. This research explores the use of a neural network modeling and genetic algorithm optimization method with these different datasets. The focus is on a high-aspect-ratio etch process across the different fabs and production stages. Models are built from process input variables to post-process metrology, and from process input variables to yield metrics. In the latter case, there can be tens of processes occurring between the model input and output variables. I demonstrate the usefulness and industrial application of neural network process modeling and genetic algorithm recipe optimization by performing a reaction chamber matching exercise on a manufacturing line. The performance of a reaction chamber can deviate from target, either in terms of its post-process metrology or its associated yield metrics. The method developed herein generated an optimized recipe that brought the outlying behavior of a chamber closer to target and closer to that of the other chambers (“chamber matching”). This is one of many possible applications. It was chosen because it demonstrates both the fidelity of the process models and the effectiveness of the optimization algorithm.
dc.description.degree Ph.D.
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/53382
dc.publisher Georgia Institute of Technology
dc.subject
dc.subject Semiconductor manufacturing
dc.subject Neural networks
dc.subject Machine learning
dc.subject Process modeling
dc.subject Process control
dc.subject Chamber matching
dc.title Process modeling and optimization using industrial semiconductor fabrication data
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
thesis.degree.level Doctoral
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
MEVAWALLA-DISSERTATION-2015.pdf
Size:
35.13 MB
Format:
Adobe Portable Document Format
Description:
License bundle
Now showing 1 - 2 of 2
No Thumbnail Available
Name:
LICENSE_1.txt
Size:
3.87 KB
Format:
Plain Text
Description:
No Thumbnail Available
Name:
LICENSE.txt
Size:
3.87 KB
Format:
Plain Text
Description: