Title:
Architectural Support for Protecting Memory Integrity and Confidentiality

dc.contributor.advisor Lee, Hsien-Hsin Sean
dc.contributor.author Shi, Weidong en_US
dc.contributor.committeeMember Ahamad, Mustaque
dc.contributor.committeeMember Cui, Weidong
dc.contributor.committeeMember Giffin, Jonathon
dc.contributor.committeeMember Schwan, Karsten
dc.contributor.department Computing en_US
dc.date.accessioned 2006-09-01T19:05:10Z
dc.date.available 2006-09-01T19:05:10Z
dc.date.issued 2006-05-10 en_US
dc.description.abstract This dissertation describes efficient design of tamper-resistant secure processor and cryptographic memory protection model that will strength security of a computing system. The thesis proposes certain cryptographic and security features integrated into the general purpose processor and computing platform to protect confidentiality and integrity of digital content stored in a computing system's memory. System designers can take advantages of the availability of the proposed security model to build future security systems such as systems with strong anti-reverse engineering capability, digital content protection system, or trusted computing system with strong tamper-proof protection. The thesis explores architecture level optimizations and design trade-offs for supporting high performance tamper-resistant memory model and micro-processor architecture. It expands the research of the previous studies on tamper-resistant processor design on several fronts. It offers some new architecture and design optimization techniques to further reduce the overhead of memory protection over the previous approaches documented in the literature. Those techniques include prediction based memory decryption and efficient memory integrity verification approaches. It compares different encryption modes applicable to memory protection and evaluates their pros and cons. In addition, the thesis tries to solve some of the security issues that have been largely ignored in the prior art. It presents a detailed investigation of how to integrate confidentiality protection and integrity protection into the out-of-order processor architecture both efficiently and securely. Furthermore, the thesis also expands the coverage of protection from single processor to multi-processor. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 1873667 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/11460
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Anti-reverse engineering en_US
dc.subject Secure processor
dc.subject Memory protection
dc.subject.lcsh Computer storage devices en_US
dc.subject.lcsh Data encryption (Computer science) en_US
dc.subject.lcsh Computer security en_US
dc.title Architectural Support for Protecting Memory Integrity and Confidentiality en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.corporatename College of Computing
relation.isOrgUnitOfPublication c8892b3c-8db6-4b7b-a33a-1b67f7db2021
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