Design of power delivery networks for noise suppression and isolation using power transmission lines

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Huh, Suzanne Lynn
Swaminathan, Madhavan
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In conventional design of power delivery networks (PDNs), the PDN impedance is required to be less than the target impedance over the frequency range of interest to minimize the IR drop and to suppress the inductive noise during data transitions. As a result, most PDNs in high-speed systems consist of power and ground planes to provide a low-impedance path between the voltage regulator module (VRM) and the integrated circuit (IC) on the printed circuit board (PCB). For off-chip signaling, charging and discharging signal transmission lines induce return currents on the power and ground planes. The return current always follows the path of least impedance on the reference plane closest to the signal transmission line. The return current path plays a critical role in maintaining the signal integrity of the bits propagating on the signal transmission lines. The problem is that the disruption between the power and ground planes induces return path discontinuities (RPDs), which create displacement current sources between the power and ground planes. The current sources excite the plane cavity and cause voltage fluctuations. These fluctuations are proportional to the plane impedance since the current is drawn through the PDN by the driver. Therefore, low PDN impedance is required for power supply noise reduction. Alternatively, methods of preventing RPDs can be used to suppress power supply noise. Using a power transmission line (PTL) eliminates the discontinuity between the power and ground planes, thereby preventing the RPD effects. In this approach, transmission lines replace the power plane for conveying power from the VRM to each IC on the PCB. The PTL-based PDN enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed, unlike the power-plane-based PDN. As a result, a closed current loop is achieved, and the voltage fluctuation caused by RPDs is removed in idealistic situations. Without the RPD-related voltage fluctuation, reducing the PDN impedance is not as critical as in the power-plane-based approach. Instead, the impedance of the PTL is determined by the impedance of the signaling circuits. To use the PTL-based PDN in a practical signaling environment, several issues need to be solved. First, the dc drop coming from the source termination of the PTL needs to be addressed. The driver being turned on and off dictates the current flow through the PTL, causing the dc drop to be dynamic, which depends on the data pattern. Second, impedance mismatch between the PTL and termination can occur due to manufacturing variations. Third, an increase in the number of PCB traces should be addressed by devising a method to feed more than one driver with one PTL. Lastly, the power required to transmit 1 bit of data should be optimized for the PTL by using a new signaling scheme and adjusting the impedance of the signaling circuit. Constant flow of current through the PDN is one solution proposed to address the first two issues. Constant current removes the dynamic characteristics of the dc drop by inducing a fixed amount of dc drop over the PTL. Moreover, constant current keeps the PTL fully charged at all times, and thereby eliminates the process of repeatedly charging and discharging the power transmission line. The constant current PTL (CCPTL) scheme maintains constant current flow regardless of the input data pattern. Early results on the CCPTL scheme have been discussed along with the measurements. The CCPTL scheme severs the link between the current flowing through the PTL and the output data of the I/O driver connected to it. Also, it eliminates the charging and discharging process of the PTL, thereby completely eliminating power supply noise in idealistic situations. To reduce any associated power penalty, a pseudo-balanced PTL (PBPTL) scheme is also proposed using the PTL concept. A pseudo-balanced (PB) signaling scheme, which uses an encoding technique to map N-bit data onto M-bit encoded data with fixed number of 1s and 0s, is applied. When the PB signaling scheme is combined with the PTL, the jitter performance improves significantly as compared to currently practiced design approach.
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