Person:
Bakir, Muhannad S.

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Now showing 1 - 7 of 7
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    Interconnects, System Integration, and Packaging of Electronics
    ( 2014-08-21) Bakir, Muhannad S.
    This presentation will provide a retrospect and prospects for electronics interconnects, system integration, and packaging.
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    3D Integration: A New Era for the Integrated Circuit
    (Georgia Institute of Technology, 2010-03-30) Bakir, Muhannad S.
    The information revolution has been the most important economic event of the past century and its most powerful driver has been the silicon integrated circuit (IC). Over the past fifty years, the migration from BJT to CMOS technology combined with transistor scaling has produced exponential benefits in microchip productivity and performance. However, as silicon technology progresses beyond the 45 nm node, the performance of a system-on-a-chip (SoC) has lagged by progressively greater margins to reach the intrinsic limits of each particular generation of technology. A root cause of this lag is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high performance SoC, especially in areas of cooling, off-chip signaling, and power delivery. The need for ever greater off-chip bandwidth will be especially problematic as the number of cores on a microprocessor increases. Revolutionary "silicon ancillary technologies" are needed to address these challenges. Of course, innovation in silicon ancillary technologies will have to be done in parallel with continued innovations at the chip level (improved scaled transistors and interconnects) as well as system architecture among other things. Three-dimensional (3D) system integration can be used to greatly enhance communication between ICs (larger bandwidth, lower latency, and lower energy per bit) as well as enable heterogeneous integration of technologies. However, 3D IC technology also presents challenges. Aside from issues relating to manufacturing, power delivery and cooling of a stack of logic chips presents many challenges. Simply put, it is difficult enough to cool and deliver power to a single processor today. Stacking multiple processors and memory chips, for example, presents formidable challenges that require advanced silicon ancillary technologies. These issues will be discussed in the seminar. This presentation will also discuss the unique opportunities and technologies for 3D heterogeneous integration of CMOS electronics with chemical and bio-sensors.
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    Chip-level waveguide-mirror-pillar optical interconnect structure
    (Georgia Institute of Technology, 2006-07) Ogunsola, O. O. ; Thacker, H. D. ; Bachim, B. L. ; Bakir, Muhannad S. ; Pikarsky, J. ; Gaylord, Thomas K. ; Meindl, J. D.
    Waveguides, mirrors, and polymer pillars can be integrated together to provide optical interconnects to the chip level. Total internal reflection in the polymer pillar provides a high level of spatial confinement of the light. The metallized mirror terminating the waveguide may be at 45 or at a nearby angle such as 54.74 (anisotropically etched silicon) and produce nearly equal coupling efficiencies. For a polymer waveguide, a gold mirror, and a polymer pillar of the dimensions fabricated, the simulated coupling efficiencies are 80.7% or 0.93 dB (45 mirror) and 82.5% or 0.84 dB (54.74 mirror), respectively. These simulations together with the fabrication and testing of a 54.74 mirror configuration demonstrates the viability of the waveguide-mirror-pillar structure, its insensitivity to mirror angle, and its compatibility with current substrate fabrication technologies.
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    Optical transmission of polymer pillars for chip I/O optical interconnections
    (Georgia Institute of Technology, 2004-01) Bakir, Muhannad S. ; Gaylord, Thomas K. ; Ogunsola, O. O. ; Glytsis, Elias N. ; Meindl, J. D.
    In the pursuit of high-density wafer-level input–output optical interconnections, microscopic polymer pillars have recently been fabricated. The optical performance of these pillars is critical for their potential application to gigascale integration. In the present work, the optical transmission of these pillars is analyzed and measured. It is shown that these polymer pillars act as precision many-moded waveguides, thus, verifying the cross-sectional uniformity, smoothness of surfaces, and optical quality of the material.
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    Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration
    (Georgia Institute of Technology, 2003-12-01) Bakir, Muhannad S.
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    Sea of polymer pillars: Compliant wafer-level electrical-optical chip I/O interconnections
    (Georgia Institute of Technology, 2003-11) Bakir, Muhannad S. ; Gaylord, Thomas K. ; Martin, Kevin P. ; Meindl, James D.
    An electrical–optical chip input–output (I/O) interconnection technology called sea of polymer pillars (SoPP) is presented. SoPP provides highly process-integrated and mechanically flexible (compliant) electrical–optical die-to-board interconnections that mitigate thermo-mechanical expansion mismatches. The I/O density of SoPP exceeds 10⁵ /cm². The compliance of the polymer pillars is shown to be 3–5 µm/mN. Approximately 50% input optical coupling efficiency into a volume grating coupler through a set of polymer pillars is demonstrated.
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    Chip-to-Module Interconnections Using "Sea of Leads" Technology
    (Georgia Institute of Technology, 2003-01) Bakir, Muhannad S. ; Reed, Hollie A. ; Mulé, Anthony V. ; Jayachandran, Joseph Paul ; Kohl, Paul A. ; Martin, Kevin P. ; Gaylord, Thomas K. ; Meindl, James D.
    The drive toward higher density and higher performance in integrated circuits creates a need to keep interconnects short and eliminate layers of packaging. In this article, we propose a novel, ultrahigh-density (exceeding 10⁴leads per cm²), compliant, wafer-level, input/output interconnection technology called "sea of leads" as a key enabling technology for future high-performance microsystems. The mechanical compliance is addressed through slippery leads (leads released from the surface) and embedded air gaps.The ability to fabricate embedded air gaps has enabled the integration of optical interconnects with high index-of-refraction mismatches between the core and cladding.