Mukhopadhyay, Saibal

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Now showing 1 - 3 of 3
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    Energy Introspector: Coordinated Architecture-Level Simulation of Processor Physics
    (Georgia Institute of Technology, 2013) Song, William J. ; Mukhopadhyay, Saibal ; Rodrigues, Arun ; Yalamanchili, Sudhakar
    Increased power and heat dissipation in microprocessors impose limitations on performance scaling. Power and thermal management techniques coupled with workload dynamics cause increasing spatiotemporal variations in electrical and thermal stresses. The coupling between various physical phenomena (e.g., power, temperature, reliability, delay) will be critical to microarchitectural operations in future processors. Thus, we need modeling tools to enable the exploration of such physical interactions and drive development of microarchitectural solutions. This paper introduces a novel framework, Energy Introspector (EI), for the coordinated simulation of microarchitecture and physics models. The EI framework features flexible modeling of processor component hierarchy that enables simulating different microarchitecture and package designs. The proposed framework uses standardized interface to drive different implementations of physics models and captures their interactions. The EI supports parallel computation of models in anticipation of large-scale simulations (e.g., high core-count processors). We present a case study using the EI framework to assess reliability and performance tradeoffs with a full-system cycle-level simulation of an asymmetric chip multiprocessor (ACMP).
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    Design of low-power wireless electroencephalography (EEG) system
    (Georgia Institute of Technology, 2011-07-01) Mukhopadhyay, Saibal
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    System Impact of 3D Processor-Memory Interconnect: A Limit Study
    (Georgia Institute of Technology, 2011) Rasquinha, Mitchelle ; Hassan, Syed Minhaj ; Song, William ; Chae, Kwanyeob ; Cho, Minki ; Mukhopadhyay, Saibal ; Yalamanchili, Sudhakar
    3D integration with through-silicon-vias (TSVs) can provide enormous bandwidth between processor die and memory die. The central goal of our work is to explore the limits of performance improvement that can be achieved with such integration. Towards this end we propose a model of the impact of 3D TSVs on system performance. The model leads to several key observations i) increased miss tolerance (smaller caches) and hence improved core scaling for a fixed die size, ii) higher sustained IPC per core, iii) significantly smaller, energy efficient DRAM banks, iv) redistribution of system power to the cores and on -die interconnect, and v) TSV utilization is a function of the relationship between reference locality and the bandwidth properties of the intradie network. These observations are repeated in cycle level simulations of a 64 tile architecture.