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Prvulovic,
Milos
Prvulovic,
Milos
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ItemUnderstanding, Alleviating and Exploiting Electro-Magnetic Side-Channel Signals(Georgia Institute of Technology, 2016-09-16) Prvulovic, Milos ; Georgia Institute of Technology. Institute for Information Security & Privacy ; Georgia Institute of Technology. College of ComputingA side-channel attack is an attack that exploits the low-power electronic signals a device emits even when it’s not connected to the Internet or a network. Such signals can leak sensitive data used in a computational task. Among side channels, the electromagnetic emanations are particularly interesting because they do not require any contact with the target device in order to read potentially sensitive and private data. While side-channel attacks can be conducted without understanding the relationship between computation and electromagnetic emanations, prevention is usually cost-, overhead-, power- and/or weight-intensive. In this talk, I will describe our work to understand the execution-emanations relationship, how this research can be used to "surgically" alleviate side-channel vulnerabilities, and even how it enables new beneficial uses of side-channel information.
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ItemTowards Optimal Power Management: Estimation of Performance Degradation due to DVFS on Modern Processors(Georgia Institute of Technology, 2010) Amur, Hrishikesh ; Prvulovic, Milos ; Schwan, Karsten ; Georgia Institute of Technology. College of Computing ; Georgia Institute of Technology. Center for Experimental Research in Computer SystemsThe alarming growth of the power consumption of data centers coupled with low average utilization of servers suggests the use of power management strategies. Such actions however require the understanding of the effects of the power management actions on the performance of data center applications running on managed platforms. The goal of our research is to accurately estimate power savings and consequent performance degradation from DVFS and thereby better guide the optimization of a performance/power metric of a platform. Towards that end, this paper presents precise performance and power models for DVFS strategies. Precise models are attained by better modeling the performance behavior of modern out-of-order processors, by taking into account, for instance, the effects of cache miss overlapping. Models are validated using benchmarks from the SPEC CPU2006 suite, which show that the observed degradation always falls within the predicted bounds. Also, the upper bound degradation estimates were up to 43% less than those due to a linear degradation model which allows for the aggressive use of DVFS.
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ItemPerformance debugging support for many-core processors project(Georgia Institute of Technology, 2012-09) Prvulovic, Milos ; Oh, Jungju ; Park, Sunjae ; Georgia Institute of Technology. Office of Sponsored Programs ; Georgia Institute of Technology. School of Computer ScienceIn recent years, the number of cores available on a processor has increased rapidly, while the performance of an individual core has increased much more slowly. As a result, achieving a large performance improvement for applications now requires programmers to leverage the increased core count. This is often a very challenging problem, and many parallel applications end up suffering from performance bugs caused by scalability limiters. These prevent performance from improving as much as it should with more cores. Since we expect core counts to continue increasing for the foreseeable future, addressing scalability limiters is important for developing software that will obtain better performance on future hardware. This project, jointly funded by SRC and NSF, investigated software and hardware mechanisms that automate significant parts of this performance/scalability debugging effort in order to give programmers accurate and actionable feedback about the scaling limiters present in their code. Scalability limiters are mostly caused by resource-related bottlenecks and by insufficient exposed parallelism in the application. The main resource-related bottlenecks are related to excessive cache misses, while insufficient parallelism is mostly manifested as threads waiting to complete a synchronization operation such as a lock (lock contention) or a barrier (load imbalance).
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ItemCAREER: Architectural Support for Parallel Execution as a Continuum of Transactions (ASPECT)(Georgia Institute of Technology, 2010-07-09) Prvulovic, Milos ; Georgia Institute of Technology. Office of Sponsored Programs ; Georgia Institute of Technology. College of Computing
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ItemKIMA: Hybrid Checkpointing for Recovery from a Wide Range of Errors and Detection Latencies(Georgia Institute of Technology, 2010) Doudalis, Ioannis ; Prvulovic, Milos ; Georgia Institute of Technology. College of Computing ; Georgia Institute of Technology. School of Computer ScienceFull system reliability is a problem that spans multiple levels of the software/hardware stack. The normal execution of a program in a system can be disrupted by multiple factors, ranging from transient errors in a processor and software bugs, to permanent hardware failures and human mistakes. A common method for recovering from such errors is the creation of checkpoints during the execution of the program, allowing the system to restore the program to a previous error-free state and resume execution. Different causes of errors, though, have different occurrence frequencies and detection latencies, requiring the creation of multiple checkpoints at different frequencies in order to maximize the availability of the system. In this paper we present KIMA, a novel checkpointing creation and management technique that combines efficiently the existing undo-log and redo-log checkpointing approaches, reducing the overall bandwidth requirements to both the memory and the hard disk. KIMA establishes DRAM-based undo-log checkpoints every 10ms, then leverages the undo-log metadata and checkpointed data to establish redo-log checkpoints every 1 second in non-volatile memory (such as PCM). Our results show that KIMA incurs average overheads of less than 1% while enabling efficient recovery from both transient and hard errors that have a variety of detection latencies.