Chatterjee, Abhijit

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Now showing 1 - 8 of 8
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    Robust and Reliable Error Detection and Correction for Autonomous Systems
    (Georgia Institute of Technology, 2020-01) Momtaz, Md Imran ; Chatterjee, Abhijit
    The rapid rise of self-driving cars and drones has raised questions about the safety of autonomous robotics deployed in society. This is due to the large numbers of system state variables involved, the resulting degraded ability to perform accurate error detection and most importantly, loss of the ability to perform accurate error diagnosis. Prior work on robust and adaptive control make assumptions about the boundedness of errors or require the use of full-scale system models running in the background for control reference. In this research, we show how state space checks facilitated by different machine learning algorithms can be used to detect, diagnose and compensate for errors in sensors, actuators and control program execution in linear and nonlinear systems for robotic applications. The primary focus is on low-cost, ultra-fast, efficient, and lightweight methods for mitigation of transient errors in sensor data and control program execution and parametric deviations in sensor circuitry and actuator subsystems. Additionally, the proposed approach should incur minimal hardware and software overhead. The proposed approach has been applied to multiple test-cases which includes DC motor control system, quadcopter as well as automotive subsystems such as steer by wire subsystem. Simulation results indicate that errors can be compensated with high efficiency and low computation overhead.
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    Adaptive FPGA-based Test Module
    (Georgia Institute of Technology, 2013-05-30) Chatterjee, Abhijit ; Keezer, David C.
    The objective of the project is to develop methods and electronics for testing multi-GHz digital components (such as DDR memories), using low-cost methods based on state-of-the-art field programmable gate arrays (FPGAs). A further objective is to incorporate the means for the test electronics to “self-monitor” its own performance, and to “adapt” its behavior (performance) in order to optimize the quality of the test signals. Therefore this project seeks to realize two major benefits as compared to traditional testing methods: (1) lower test equipment cost and (2) improved test signal quality (especially for high-speed signals). This report describes the activities and preliminary results obtained during the first six months of this project.
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    Targeting multi-core clock performance gains: vertically integrated adaptation and prototyping
    (Georgia Institute of Technology, 2012-06) Chatterjee, Abhijit
    A low cost post-manufacturing testing and speed tuning methodology is proposed in a multi-processor system. The goal of this research is to develop a methodology that allows the “safe” speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures.
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    Optimal linearity testing of sigma-delta based incremental ADCs using restricted code measurements
    (Georgia Institute of Technology, 2010-11) Chatterjee, Abhijit ; Kook, S. ; Gomes, A. ; Jin, L. ; Wheelright, D.
    Linearity testing of high-precision (beyond 20-bit resolution) Analog-to-Digital converters (ADCs) is extremely expensive due to the large number of codes (>16 million for a 24-bit converter) that need to be tested and the associated low data rates making traditional histogram based testing infeasible. Industry often performs linearity test for such high-precision data converters with significantly reduced numbers of code measurements during production test. Given a specified allowed number of code measurements, the problem is to determine the requisite code points that result in the highest failure coverage. In this report, a methodology and tools for analyzing the “goodness” of a particular choice of test code points versus another is described. A least squares based polynomial fitting approach using measurements made at selected test code points is used to characterize the transfer function of the ADC for INL (Integral Nonlinearity) error. In addition, the characteristics of devices that may escape from the proposed approach (test escapes) are revealed for the specified test via an optimization based search technique. Software simulations are performed to study and validate the proposed methodology.
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    Final report: optimal linearity testing of Sigma-Delta based incremental ADCs using restricted code measurements
    (Georgia Institute of Technology, 2010-05-31) Chatterjee, Abhijit ; Kook, S. ; Gomes, A. ; Jin, L. ; Wheelright, D.
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    Signal acquisition of high-speed periodic signals using incoherent sub-sampling and back-end signal reconstruction algorithms
    (Georgia Institute of Technology, 2009-02) Chatterjee, Abhijit ; Gomes, Alfred V. ; Choi, Hyun
    This paper presents a high-speed periodic signal acquisition technique using incoherent sub-sampling and backend signal reconstruction algorithms. The signal reconstruction algorithms employ a frequency domain analysis for frequency estimation, and suppression of jitter-induced sampling noise. By switching the sampling rate of a digitizer, the analog frequency value of the sampled signal can be recovered. The proposed signal reconstruction uses incoherent sub-sampling to reduce hardware complexity. The results of simulation and hardware experiments indicate that the proposed signal reconstruction algorithms are able to reconstruct multi-tone high-speed periodic signals in the discrete time domain. The new signal acquisition technique simplifies signal acquisition hardware for testing and characterization of high-speed analog and digital signals.
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    Low-cost testing of ADCs and DACs
    (Georgia Institute of Technology, 2006-12-01) Chatterjee, Abhijit ; Goyal, Shalabh
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    Hierarchical Power Optimization for System-on-a-Chip (SoC)through CMOS Technology Scaling
    (Georgia Institute of Technology, 2002) Choi, Kyu-Won ; Chatterjee, Abhijit
    This report describes an efficient hierarchical design and optimization approach for ultra-low power and minimum area CMOS logic circuits in a system-on-a-chip (SoC) design environment. For state of the art systems, the trade-off solutions between the conflicting design criteria (Delay, Area, and Power) should be considered. In this report, we consider interactions between abstraction levels of the design hierarchy and present techniques that co-optimize the power and the area without performance degradation through judiciously explored technology parameters: Supply voltage, Threshold voltage, and Device width. Experimental results deliver over an order of magnitude savings in power over conventional optimization methods.