Great thank you very much Kevin for
the introduction and thanks to honk and

I for hosting me it's a real
pleasure to be here and

I am absolutely stunned
by the strong turnout.

I want to think it's really of my
topic that has excited that so

many a few but
part of me really feels it's a lunch.

That provided has something to do with
this but I'm really really very happy and

really on there to have your time for
the next fifteen minutes or so.

So.

The title of my talk is interconnect
system integration package and offer one

to our next and that's really sort of
the topic that we focus on in my group.

So before I begin I have to
acknowledge my group members

we currently consist of
twelve graduate students.

All pursuing their Ph D.'s.

And almost recent picture of
us at lunch is showing here.

And the topics that we can afford us and

my group are listed here one is we
look a lot into how do you build three

dimensional integrated circuits and
also a little bit of of that later.

We also look in developing and integrating
as Venice called solutions with high end.

And high power processors.

We certainly do a lot of work
in advanced packaging and

there were beginning to do some work in
that staffing for silicon photonics as all

us for electronics using into a port of
technology which I'll talk about a little

bit later and then finally of course
all the technology development we do is

guided by modeling and benchmarking.

And feel like the bit more information
including some of her recent publications

that can be shot at on our website and

then I kind of want this
just to really highlight.

Some of the people in my group because.

You know the people who
really do all the great work.

And the reason we've been
productive as Kevin pointed out is

because we have a group of people that
are very talented very determined to make

an impact in the field and that's really
what matters the most and so here

I've just highlighted in the last you some
of the words of my students have received.

Which is you know the most gratifying
part of my job which is to see

people working with you get recognized for
they do that's really.

Nothing brings me joy as much as
seeing my group members doing well.

And so that includes people some
very prestigious fellowship

as was paper towards.

OK so
I want to dive in to the topic at hand and

the topic at hand deals with how do you
build computing systems in the future.

One of the key important things
when you design a high end

computing system is look at the band
with needs meaning the total or

the aggregate signal in back to
us you need between components

most mostly between logic and memory.

And this is a very significant plot this
is a plot that shows the total meaning

aggregate total after
band with versus year.

And the plot over here is really that
blind over here is a one that we

really should focus our attention on
what that shows is on this lot scale

the band with total band with
after it has been increasing

in the trend showing here.

If I look at this data point
approximately over a year and

this data point over here what this shows
is that after a band of has increased

by one hundred times over
the last essentially decade or

so after Bennett has increased by one
hundred X. over the last ten years.

The projection is is that we're definitely
going to keep going from that trip so

I need more and more of the.

Band with between logic and

memory there's absolutely no slowing down.

OK Now how how does
after band with help us.

So the plot shown here is
a system throughput so

system throughput means
instructions per cycle essentially.

And in this case the units are billions
that's why they have be billions

I stands for instructions pieces for.

Their instructions per second so
that's I P S And

what we see is here is a plot
showing you system through put.

Forward two different.

Off chip data rates in one case
we're being limited to fifty

bigger bytes per second and other peers
who are being limited to one hundred

gigabytes per second.

And the really important takeaway message
from the used to curve here is that

by us finding a way to increase
after a band with we can

improve system throughput meaning I
can do more instructions per side.

So I can do more computations
per unit of time as

we increase the data rate.

And this trend again will
simply become more and

more important in the future
we need more bandwidth.

But here is a problem and
that problem is shown on the right side.

This is a chart of Python
showing you the top top

power dissipated in the microprocessor.

And what we see is that that.

After chip interconnect
the bandwidth on through.

Interconnect power is typically limited
to around anywhere between ten to maybe

twenty percent of the Tortola aggregate
power you can dissipate in the process.

And in fact it's sort of projected
that for the next number of years.

Processor power will
essentially remain constant.

OK And so if I am restricted
to a fixed power budget.

How will I in the future continue
to increase my after band.

It takes energy to send information
across the system and so

if all the study you want to double the
information you send across a system bump

telling you you can't use any
more power that's a problem.

There.

And so what is the solution that everyone
now in the world is going after.

Well the only way you can continue
to increase a band with but

at the fix power budget is to
improve the energy efficiency.

Of data transmission.

In other words now you
have to find ways or

fusing you know sending a bit across
the system but doing it to a plus power.

So that's really the name of the game
today is improving in the E.G. efficiency.

Why again because we will restrict
it to a certain power budget and

I keep doubling my bandwidth every so
years.

So I need to find ways to send
information across a system with less and

less and less power as we go forward.

So how do you do that well there is in the
world we could say we should come up with.

Circuits to transmit information
which is fine but to a transistor for

improved in the deficiency but the real
thing that will make the most difference

is if we find new interconnects
through rock trees.

That are a lot lower lots.

To transmit that information.

And so this is where this is
really an area that is incredibly

now active in research which
is finding better why are so

if you would to transmit
information across the system.

OK.

So ones that can certainly give
me the data rates I need but

efficiency that I want.

So the kind of research that's
going on in in the field

really consists of people looking
at sort of electrical solutions and

people looking at kind of tonic solutions.

To the way we build systems a sort of
somewhat Shaun of the schematic so

the way we do things today is we
take two silicon chips or two.

You know a logic and a memory chip
we place them on organic package and

we use the wires on the organic
package to crew year the signals.

The problem is.

One the density of wires you have one and

there again a package are pretty a lot
that density is a very low value and

so you can't really have enough channels
to begin with and second the energy that's

required in translating that information
is fairly high using this method.

And so one think our.

So one thing that people
are looking at now is act.

Really Are there using.

A fiber ribbon if you would between two
packages to connect them up to CLI or

actually use flexible copper wires to
connect to a different package substrates.

But most of the research that's really
happening today Cana at this from

the other two call domain
is was showing here.

The idea there is join here is actually
fairly simple very disruptive.

The idea is hey wide on why don't
time mount my logic and memory chips.

On actually another Silicon Chip.

And the other silicon chip is typically
referred to as into ports or today.

So this grey layer here is
actually a silicon chip.

Except it doesn't have active devices
It does however have the very dense.

A lock to call interconnects that
are needed in able very high bandwidth

density communication.

OK.

So this is an area called silicon
interposer technology and

there's certainly a lot of research going
on in this area the main limiter with this

approach is of course cost is an important
limiter making a large silicon

chip even though it's passive meaning no
transistors on there it's pretty costly.

So that's one issue and
the second issue is that.

The wires that you end up building even
though they're very fine which gives you

the large density of connections is that
they tend to be pretty resistive and

therefore very last see
a sufficiently long glance.

So for this to work really well
you've got to have things.

Very costly each other.

Now some of the other things that
people are doing Shawn here and

I kind of focus on this for the sake
of time what people are looking at

is trying to integrate
silicon photonics So meaning.

So they can based waveguides on this.

Into a pause or a platform.

And so that you can fat sent optical
signal across the interposer system.

At hopefully what people are flowing
much lower energy per bit.

And much higher bandwidth their cities.

I lost my microphone.

Or it.

So I sort of wanna share with you
some of the work we're doing and

in trying to solve this problem.

So the vision for

some of the research we're doing in micro
begins with the following schematic.

So I recall in the previous slide I said
well what people are doing is they're

mounting chips on interposer and
there's interpose of course mounted on

the organic package that again
within goes to the mother.

What we want to do is we want to think
about how do you build larger scale.

Systems based on solid can interposer
technology you know what's

really good about what you see here is
that you know all of these solutions for

example this solution this will be these
are things that work in a pretty world

within the into ports or footprint but
the moment I want to scale this meaning at

the moment I want to build a supercomputer
where may have one hundred thousand A-C.

logic units on there how do you
scale this how do we extend the bed.

The fits within this into a pause or
two beyond into a pause or footprint.

So our solution to solving
this problem is shown here so

the first thing we do is we actually.

Get rid of the package.

And we say you know what that
package is really not necessary.

And so what we do is we take that
silicon interposer we build mechanically

flexible interconnects on there which
I'll talk about little bit later.

And then I'm out my silicon interposer or

silicon tile as we call
a director on the motherboard.

So the benefits of this will become
apparent in the next few slides.

Next what we do.

Is we actually build these self alignment
structures on the motherboard so

what we do is we build these semisphere
directors on the motherboard and

we build these inverted pyramid in
the silicon and so just like in Lego's.

We can essentially put the interposer
down of the motherboard

in a very well in a way
similar to building.

The beauty of this or to force one it
really simplifies assembly process right

all you do is you drop the entry points of
the motherboard shake things around and

it automatically assembles in the right
spot the second thing is a gives you

precise alignment control that you could
otherwise not do with the flip to ponder.

OK.

Then what we do is like
OK why don't we now.

Assemble another Silicon interposer or
silicon tile next to it.

And then.

Bridge it.

With a third so.

Substrate.

And so
at the end what this allows us to do now

is to build a large
scale solar can system.

In which I can have them electrical and

as also for
panic wires not just within one tile but

once can that can bridge over to nearby
interposes if I did not have this

bridge structure in here the question
is how will my components

over here communicate with
my components over here.

If the answer is Well we have to
go through the motherboard and

come back up there and you've come to
last a lot of energy in doing so and

you've lost a lot of bench you cannot
support high Danders on the market period.

It's very child I mean there's a bit
more to the story but for now.

You know achieving high bandwidth
with a motherboard is tough and

the energy can be especially for
a longer distance can be challenging so

are solutions is to say why don't
they use a third silicon layer

to continue the dance copper wires and my.

For tonic components that I'll
talk about in just a list second.

So just to kind of give you images of
things we fabricated now by the way I

should say all fabrication results you see
here are all done in georgia tech clean

rooms for the ones in the Marcus
building which is where we are today and

the one in the pattern building.

So my SO structures are showing here
the Semisphere structure is shown in this

image my inverted pyramid structure
which is in the tile is shown over here.

And the dimensions of these
structures are sort of.

You know this is about
three hundred microns.

And the with ears and one hundred microns
and the way this works is sort of shown in

this kind of simple animation which is
intercourse or simply comes down and

even it's misaligned with respect to
the software and structure is if you just

shake things around it will
automatically fall into place.

And the way we fabricate these.

Mysterious structures is we take a silicon
wafer or in this case a motherboard

we spend called a forth to
resist layer we apply heat

by applying heat that causes a surface
tension effects that cause the original

surface to make a very nice for coal ship.

And then we do some post-processing
on this to ensure reliability and

other things.

And here are just some
characterization results proving that

the structures we fabricate indeed are.

Spherical in shape and
we've kind of compared and

a microscope measurement to
an actual semisphere structure and

they kind of match perfectly.

So a question is how good is the alignment
how little fellow can they get between

two tiers using what I just showed you.

So if I'm assembling a silicon chip on
the glass layer my alignment can be

better than one micron.

If I'm doing it on so
they can again I can achieve better than

one micron accuracy the reason we
can't give an exact number below

one Mark is simply we just don't have a
really good way of measuring that value so

it could be a lot better than one
micron but we just don't have.

The confidence to share that number so
we know it's below one micron.

Now when you assemble on printed
circuit board like an effort for

a structure so everyone here I'm sure
has seen a printed circuit board and

we all know that the surface is
pretty rough and it's not planar and

therefore by doing so you can induce
a bit more misalignment and so

by doing these alignment measurements
of silicon on effort for

we can achieve at the moment alignment
accuracy about three microns or

about four microns worst case scenario.

I think we have ideas of trying to
improve that number to smaller values.

So.

These little red structures shown here are
our mechanically flexible interconnect So

what does that mean these are essentially
my course brings we fabricate

between the silicon layer and
the motherboard and S.C.M.

image of these micro
Springs is shown here.

I think these are on our I would say
maybe one hundred fifty my compared to

approximately.

And I know we have some images of
a bit later but each of these things

these S. shaped structures to represent
one electrical interconnect and

these springs are very very deformable So
if I apply a little bit force at the tip.

These structures will do form down
significantly how significant Well

we've already demonstrated the ability
to bend down almost by sixty markings

which to my knowledge is one of
the highest values shown for

any sort of flexible interconnect.

Now the reason these flexible interconnect
is because silicon and effort for

obvious I mean are two different
materials of the city mismatch is

also like I said the motherboard is
very non planar And so to make rube.

First contact to an interposer we
need something that can sort of

deformed with the wave of the surface and
this flexible and

you can sort of a perfect
solution to that.

Now we also have another set of flexible
interconnect that we use in this region.

Now the density of the flexible or to
connect down here is limited by the pitch

of the wire as you can make
on the motherboard and

I think best value is around two
hundred micron However up here

remember this is silicon technology so
I can have extremely find connections and

therefore in this region I use very
dense flexible interconnect so

that I can maintain the large band
with connectivity between my tears.

And so even even though these and
these are fabric exactly same way and

one case we choose to do very low density
to match the density of what is over

here in other case we choose
to use very high density

on the surface to match the density
of a sea of the wires there.

And they ultimately the vision is
to ultimately fabricate silicon for

tonic with guys with diffract of
grating couplers to enable for

tonic connectivity across a very large so
we can interconnected system.

And so
this is where we would like to go and

I was going sort of as future research.

So I want to say a little bit about
alignment so why is alignment so

critical Well I'm it is so critical
because if I choose to build it for

tonic link in which one have a waveguide

sort of bridge between two and
three posers.

Turns out unfortunately the coupling
efficiency between one for

tonic layer and the other is
highly dependent on how world.

You kind of line them together.

OK if I have really good alignment my
excess losses are going to be lower.

And so here is some data
taken out of these papers and

what the essentially essentially show
is the excess lost coupling efficiency

versus mis online math between two
diffract of creating elements.

And what we see is that if we have a
misalignment of approximately two microns

or less if we microns my excess.

Loss in the photonic link
can be another two D.B.S..

And so what this basically
means it's very important for

us to invent structures that can give
me extremely high accuracy alignment.

So that I mean my losses in
transitions between my for

tonic components.

Why is this important world's
all about energy remember

at the end of the day a company like into
will tell you hey you have only ten what

you give me this data rate you figure it
out so you're going to have to find every

single way you can shave off losses.

And it actually turns out that you
know even the the silt of field of

silicon photonics is you know
sold with absolutely fantastic

work at the device level at the circuit
level the actually the amount to fork

there is in the area of interconnection
packaging and even testing is fairly

it's far less than the device level and
we talk people

to people doing research in this area they
always say that the sort of the packaging

interconnection is a challenge that
really needs to be fully addressed and so

I think here at Georgia Tech we have
an opportunity to sort of invent the key

technologies needed to enable efficient
packaging of silicon photonics.

So how good are is the work
we're doing in terms of metric.

So in other words I wonder compare
what I just showed you to what

are the alternative options
the metric we use to

demonstrate the value of a certain
interconnect structure of something

called bandwidth density
divided by energy per bit.

The larger This number
is the better it is.

We want enormous bandwidth for
zero energy ideally.

So if I put it into a pause and
by the way the assumptions are going

to making these models and so
depending on sort of how you missed.

Assumptions you'll kind of get
slightly different numbers but

the trends are nonetheless
going to be similar so

if I look at using my.

Motherboard for interposer to interpose or
electrical signalling

this is the sort of plot you would get.

If by contrast I compare this to the case
were two interposes with the other

Silicon bridge the blueline is what I
get with you is much improved bandwidth

density over in the purpose one of the
reasons obviously the Bantu a density or

the density of wires is
orders of magnitude better.

And shorter distances that works great but
unfortunately

these fine wires if you make them very
long they can actually be pretty bad and

so that's why at some point
the bridge connections become more of

their motherboard because
the losses are enormous.

Now if i use of fiber to connect things
depending on the pitch of the fiber so

we're assuming I think a picture of
about three hundred microns or so.

And because of the energy is a volved in
going electrical for tonic and vice versa

you know we think that overall
the fiber will not be.

The best solution again I think it will
offer some benefit and they gain I mean.

That yellow line whether it's really over
here or slightly above that kind depends

on some assumptions we're
doing in the modeling.

And if you again compare this to
the case we have photonic waveguides

on the motherboard.

Which people have done the problem there
is that you're limited to pretty high

values of pitch and therefore
the impacts of band of density so

again you're after you can be
somewhere maybe in this range.

And if you compare this to
the case we have silicon photonics

going from interposer to interpose or

you get roughly the line The shown here
and what that basically shows is that for

roughly shorter interconnect it's
better to do things electrically for

a little bit longer interconnects
better to go for tonic.

So that's where that crossover happens
again as a disclaimer depending on

the assumptions on what value using these
things can drift but in general the trends

are sort of the same.

So the bit about the flexible
interconnect work we're doing and

how we fabricate them.

OK so here is I think a very nice C.M.

image showing you one of these
mechanically flexible interconnects.

The height of this interface
about sixty five microns and

the person who did this work is
actually sitting in the back and

I think it's some of the best
work there is in the field.

I know you poor thing I'm biased but
it's really

some of the finest work that's
been done in this field.

These.

Structures are actually made of nickel
tungsten these are not copper electrically

these are nickel tungsten and the reason
which is nickel tanks inverses couple is

because nickel tanks has a very high yield
strength and therefore that basically

means is that I can do for my much larger
range before reaching that your strength

which means before the material
goes into plastic defamation.

But they're also coated with gold once
you make one to fabricate the nickel

tanks in structure you have to plate
you do electro less gold plating and

that's because the tungsten oxidizes and
so you get protected and

therefore you put a nicely of gold on
there and here is an optical image showing

you the gold courted nickel
tanks of flexible interconnects.

And the process we used to do this
is shown here we essentially begin

the silicon wafer patter in
this photo is this pedestal

apply heat to reflow the four to
resist put seed layer electroplate my

nickel tungsten remove the four two
is a small remove the seed layer

remove the underlying polymer dome and
then do a lot to last plating and

again every single process
step here is done at Georgia

Tech.

Grid.

So what have we done in terms of
demonstrating what I show you so

what we've actually done is we've been
able to fabricate three different

interposer tiles.

Here is number one yours number
two here is number three.

Assemble them on the motherboard
using these so structures.

Next we've been able.

To.

Apologize the response time of
the computer is a bit slow.

Next we've been able to then
assemble my bridge structures

on the silicon tiles and so
we create a can take you worst

piece of silicon there
is very large in size.

So here is tile number one thousand
number two ton number three and

here is bridge number one and
here is bridge and brittle.

And on the bridge we have the self
structures and the flexible interconnect.

So this is something no one has
ever demonstrated before and

I'm just happy to say that
Georgia Tech we're able to do this for

the first time here.

Each of these tiles is approximately
two by two centimeters and

the width of the bridge is
about six millimeters and so

in total we essentially have six by two.

So it can area ready for
assembly of components on.

Now what we did also we did some X.

ray images of the assembled sample and
this is really cool image All right so

the dark gray structure is the bridge.

So we do an extra imaging from the top
right so I'm looking down here.

That little white line.

Is actually that little tiny gap between
two edges sent silicon tiles All right so

that byte line is this little gap here.

And all this can a dense black
structure these are all my

interconnect that go from
one bridge to the other.

And in this case I think we had in
the array of four hundred or so.

So now what I.

When they do is spend limit of time
telling you what is where vision for

how each of these tires look like so
I haven't really told you what's

on the tiles of all he told you on
the build a large tire system I'm

not going to tell you why each of these
tiles is actually very unique and

has a very unique capabilities.

So.

Our vision is.

Obviously similar to what
other people are trying to do

which is we want to put integrated
circuits on a solution into a force which

again think of a silicon interposer
as a gigantic So it can chip without

active circuitry is just wired OK.

And what we would like to do is obviously
you leverage the benefits of silicon into

Poser which is essentially
the ability to have very fine

pitch wires find very fine pitch micro
bumps So for example people avoid these so

the mistress of fifty mark rampage sold
their bonds and silicon interposer and

they had two G.S.
anticipation of the functionalities.

So what we want to do is first say I want
to build actually a three dimensional

stack of integrated circuits
on the interposer And so

our idea is which again other people in
the field are also looking at is to stack

memory above one of these logic chips.

Now the challenge in doing so is that.

Delivering power and cooling of this
structure is very challenging we all

know that calling a single chip today it's
pretty hard to imagine I want to stack

multiple tips how do you remove heat.

And so our wishlist for
what we would like to do here

is sort of shown on the right side which
is essentially consists of the following

one on the find really
innovative way of do.

In cooling in this silicon
interposer slash silicon tile.

And I want to fabricate everything
including my horizontal wires as well

as my vertical wires that go through the
silicon interposer in very low cost way

methods.

And so first thing we're doing that
is unique and novel in our tiles

is we're integrating microphone channels
within the silicon interposer and

the idea is now I can pump
liquid from the into pores or

into one of my.

High powered chips so you sort of
a magnet make magnified image or

schematic I should say where
the idea is we build a little bit

interposer pump liquid from the into
Poser into the silicon chip have

the fluid go across the silicon
chip to dissipate heat.

In other words what we're doing is we're
actually building monolithic heat sinks

and silicon chips so
there is no more big air cooled heat sink

on top of a processor we've replaced
that with the idea of building tiny

fluidic channels in the Silicon.

OK.

And so how this works is kind of showing
here with this remote go back let's see

that works OK great and so then emissions
basically no you pump in cold liquid

that's represented by the blue arrows
the fluid kind of goes across the chip and

goes across the chip obvious that rejects
heat we detect He says temperature goes up

and that's where it turns into a red
arrow and one becomes hot enough to get

out of the system we've got some more away
in the system and gets called back down.

OK.

And the second thing we're doing
that is very unique and novel is.

To build Los through Silicon vias.

And the way we do this is sort of
shown here now there's an interesting

design trade of between the four with its
electrical the I would just simply skip

Well sort of hit the highlights what
we have done is we have found a way.

To etch away so we can.

Locally replace it by a polymer film.

And then make copper connections
through the polymer.

So our copper connections

that go through a silicon interposer
actually go through Parliament.

The benefits of this are multiple one it's

a much simpler fabrication process.

Than trying to actually silicon and
make vs and

to the electrical characteristics
are far superior to the losses.

Electrical losses are far superior
to the case with silicon and

we have data to prove that and
just live it so I started for

the show you the fabrication process for
how we make our polymer embedded.

So we begin the silicon wafer we at a very
big hole maybe a millimeter by millimeter.

We followed that big
hole by a polymer layer.

Then we do forty definitions of this
poem has to be forty definable and

we use forty definition to make
these deep within the polymer and

here are images of.

Vias made and polymer.

And then once you do that
we can to do a bottom up

electroplating process where once a vias
are made it just simply for the mop.

With copper and how you do that you know
there's different ways I'll talk about

some new approach we do little bit later
but the end result is something that

again Georgia Tech I'm happy to say was
the first to demonstrate which is us

taking a silicon wafer replacing a chunk
of the silicon with a six layer of polymer

the brown material he was all polymer and
you can see we have these copper layers

between four within I should
say the polymer layer and

by doing so my electrical
losses are substantially lower.

And we were the first to demonstrate this
obviously in the overall process but

also doing it at this aspect to assure we
can use very large structures silicon or

polymer for example almost three hundred
four almost four hundred micron thick and

do this process in such a late
thick layers of polymer that's

sort of pretty challenging to
do in a conventional way and

here are some measurements that we did in
our lab so here's some images from our lab

Here's an image that Pearl took of
the sample he's trying to measure

kind of hard to see but the probes
are sort of taking contact of the tears V.

and we measured up to fifty gigahertz and
there was also basically shown here.

So here are the losses.

So the.

Let's see the dashed red line
is a simulation of T.S.B.

or copper via and polymer.

The black line is the actual measured
data after the embedding and

calibration of course.

By comparison the dotted line over here is

a similar size copper of year but
made in Silicon.

So by gay with getting
rid of the silicon and

you're placing it with polymer our
losses are significantly lower.

Again why is it important
we'll just remember the very.

First you slightly said
everything is power limited.

In twenty thirty years ago when you
used to reduce you know war power

CMOS design papers they're all
looking at the wrist watches are sort

of portable of twenty but now the reality
everything in life is power limited all

the way from your cell phone to a data
center everything is power limited and

so you've got to improve
efficiency in the G. efficiency so

everything you can do to cut
down power is good news.

And of course the other thing that
we've did here is a microfluidics So

I want to spend limit of time
telling you about what we've done.

So we've invented a unique process
by which we can deliver fluid

from a silicon interposer into a chip and
that process is based

on building these unique.

Electrical and fluidic interface
structures between Silicon and

interposing and so the idea is.

To maybe actually step back so today of
course sold a marker bombs are very common

they exist in your cell phones they exist
in your laptop they exist your computers

and so this these little soldier
bumps you see here are can

a similar to what you have in your laptop
cell phone etc Except what's unique about

what I'm showing you here is actually
this sort of donut shaped structure.

This is also made out of soldier but

that structure is used to create
flow with the connection.

Between one tier and the other and

so the idea is I can use this
soldier seal if you would

to seal microphone with the channels
from the interposer to the chip.

So if you're going to start pumping
fluid in your system you better have

some really good sealing techniques or
that could be trouble.

Right and so this is why it was so
important the develop this technology.

All right the second thing we've done is
obviously build these silicon heat sink.

So what you see here is a cross
sectional image of a silicon

cylinder made on the backside of a chip.

That silicon cylinder is what ultimately
interacts with the fluid the fluid that's

being passed across the chip when
the fluid floors of crusties

silicon so
Ender's that's where the heat transfer or

the heat to move or process occurs.

Put it in another way if you open up your
desktop today you can see this really nice

big copper heat sink on
the processor right and the way

you move heat there is you have air that
goes through these big copper fence.

This is exactly the same concept except
orders of magnitude smaller This is

only two hundred microns and in height and

the steady fusing air we use a fluid.

The average damage for human hair
right is about one hundred microns.

So this is a bar to basically hairs
stacked up it's that small and

that's our heat sink.

But that's not all what we also do that so
unique is we have a way to

build copper wires through the floor
with the kids thing because you

are stacking things on top so you better
have some sort of electrical connection

that goes across the floor with this.

And so I'm going to tell a little
bit about the fabrication of this

fluidics aspect a little
bit on the measurements.

So here we show an area of this so we can.

So indoors which is my
micro heat sink here we

see the black spots which are the floor
we dig vias that feeds the fluid from

the interposer up to the chip.

And then once you do that fabrication
the other side of the chip what you do

is you obviously fabricate your electrical
microbiome So the heat sink is on one side

the Arctic America bumps on
the other side and then your.

Four WIDICK heat sink.

Is made on the again just into
the electrical connections so

here is my dense area for
trickle connections and

here we show our fluidic ceiling structure
is made in parallel to the electrical

the person who did this actually flees
here I mean this is again a first

time demonstration that Georgia Tech
is very proud to be responsible for

developing the electrical for
tonic electrical and so with the

connectivity.

OK great.

So here is an X. ray image showing you

often assemble silicon chip with
these structures in interposer.

And against as a top view image X. ray
image account without going to the details

but what you basically see so
these big black circles

are the silicon heat sink.

The small black circles are the electrical
micro bumps on the other side

of the chip so here is the electrical
heat sink and here is the.

Electrical micro bumps the black ring you

see here you see flow with Dick
micro bump and the White Hall is.

The fluid exhibitor that feeds the fluid
from the interposer to the chip.

And again we're very proud of all this X.
rays was done here at Georgia Tech.

So we've done some resistance measurements
to prove that our assembly process is

great and results basically confirm that
there are two results are very good and

then what we did also we did some
fluidic measurements where we

passed fluid into the chip and out and
we showed that we can sustain.

Very high pressure drops within
the chip without any leakage or

any problems of that nature and
that's kind of what this plant show here.

And then of course one of the important
things we've developed is we've actually

developed a process by which I make
I can make a couple of years so

the white line through a couple of years
made within one of these Florida key

things so here is a large area or a image

of my silicon so Ender's so we can
solve this remember are the heat sink.

And within the silicon cylinders you
have an airway or four by four but

if you go back one second you have
an array of four by four copper tiers vs

integrated into the heat sink.

Why do I need copper vs Well it's because
I got to connect things vertically I

connect my logic to the memory and the
dimensions of these VS is actually very

respectable value it's something
that is very very demanding and

impressive so the damage is about
twelve markers to thirty microns

in damage to in the aspect ratio
is about twenty three to one.

And I think we got knowledge Vinnie and
Gary because we

needed a lot of help in figuring out how
do you do the silicon and and they were

immensely helpful and of course you know
everything I showed you would not be

possible without the support of the clean
room staff and I am sure with others.

Support wouldn't even have done
half of the things I showed you so

it goes without saying a big thank
you to clean yourself for doing.

The very fine work that
they do every day for us.

And so I sort of want to conclude and some
new work we're doing which is trying to

explore some new ways of
doing copper filling.

So you probably didn't catch this and

because I say in the prior slides we
use sort of a bottom up plating process

where we do the plating process all
the way from the bottom of the vehicle but

up here we're looking at a process in
which you can sort of elect a plate from

the side walls of the because in theory
that could be a lot faster than a lot

better and here are some initial
work that's being done in this area.

You want the hardest things of doing this
is actually putting metal in the side

walls of the Veer And so when the people
in my group he's been looking at

doing some T. cat simulations trying
to understand what do I really need

to be doing in the clean room to get
the results I want in other words.

What is the right tool or configuration
by which I need to put my way for.

Into my P.V. P.V.
system to get a good side wall coverage.

So I really don't want to go into
detail just because of time but

it turns out you really get pay
a lot of attention to how you mount

your sample in this case when
you put in that parameter.

If you want to get a good coverage you've
put your sample at just the right angle

to get the coverage and so.

Has done some very interesting
simulations in this area and I think

what I really sort of show you sort of an
end result which is he sort of not only.

Developed.

An understanding of what you need to do in
the even the vapidity to get you know for

sidewalk coverage of a he actually
implemented this in this system so

he build the little device.

That can hold the way for you and
sort of floor tape the way for and

told as it moves around
the even the vaccination.

Now this is again where we have to say
big thank you to cleaning staff for

sort of trusting us to integrate this
system that result developed into their

even the vet system so the movies can
a sloth much faster my computers can store

on the computer over here but
essentially again with the way for

it does a sort of rotating goes towards
at different angles to make sure we have

sidewalk coverage on the side wall.

And also I think he's been doing
is he's been trying to simulate

the electroplating process and
so here is sort of our.

Illustration showing you that you
know unless you do the work to

plating at the right.

Current densities or right.

On off as a writer evolves way you may not
be able to complete the feel of the V.

And so again we're using the simulation
tools to help us understand what is it

we can do in the lab to get the results
we want and this was all very recent in

the sense that this is less than
twenty four hours old I think.

OK So I think this is a good place
to conclude So in conclusion we're

looking at a lot of interesting things and
one of them is the novel large scale and

highly scalable silicon interposer based
system will get vast cooling interposer

technologies and
we have there's of course plenty of open

questions by no means is this research
over where we're just beginning and

in addition to this we actually
have a lot of new cars.

We're doing in collaboration with a number
of faculty across campus as well as we're

beginning to cultivate some international
collaboration as with people in Europe and

so those will be some exciting things to
follow so in conclusion I need to stank.

Very important support
that we've received from

DARPA National Science Foundation
Sandia National Labs semiconductor

Research Corporation Oracle into
Lybia Global Foundries thank you very

much thank

you.

All.

So.

Yeah so actually so OK so the questions
I'll just repeat it the question is

can you explain a bit more
on the assembly process and

particularly what's physically
happening sort of as you slide or

as you put the tile on
the motherboard right.

So actually I'll be completely honest
with you I sort of had my doubts we still

we started doing this I was like I really
don't know how well this is going to work.

But of more often than not my clever

group members proved me wrong on some
things and this was one of the case where

they were able to show that
actually it is trivial process.

So sorry as some kind

of.

Yeah so.

It Through really simple process to be
completely honest with you it essentially.

It's as simple as Shaun
of this Power Point you.

The maximum initial missile I
make you can have is equal.

To the radius of the dome structure

in our case to the radius is one
hundred and fifty microns so

you can have up to an initial misalignment
of our one hundred fifty microns and

still get a perfect alignment at that and
so

how did the student do what I showed you
like the assembly actually he actually

simply uses hand he didn't use a flipped a
binder he used just tweezer he can up for

a guest where the pits are.

And then he sort of placed a kind
of shook it around a little bit and

then you can actually hear
a slight clicking noise and

we hear that clicking noise
it's perfectly aligned.

There you don't need a filter binder.

And actually one thing is we are writing
a paper now where we're actually

proposing this as a solution to
people who want to do for bonding but

don't have access to for
job on the job under is expensive and.

Yes So yeah so it turns out making
a permit in silicon is very easy

right is just another subtropics silicon.

Edge and you get those perfect right I
mean that's just along the crystal axis so

you really can't mess that one up and
the dorm

you know surface tension does this magic
and every single time you get a perfect

sphere.

OK so what we have is we
have one on each corner and

that's all you need We've not tried
to do unless I really don't know

that would make a difference but
we definitely have one in each corner and

I think sort of at the ends a balancing
force is distributed across the.

Origins.

The what I'm sorry.

Yes but the process yes way.

So botched processing is pretty
expensive time consuming for

high aspect ratio structures
I mean if you try.

It so cost is one.

Actually said important one because
ultimately the bush process also

can limit how deep a VIA is.

And so if somebody wants to do has
an application or they require a certain

depth that's beyond what the boss process
can do then you can a limited and

you have to find ways to thin down
you interpose or to make the V.A. and

actually take today's into a process
that are commercially available

there are generally about
a hundred microns thick.

One he says because of the limitations in
T.N.C. fabrication in our case we should

interpose it with four hundred
micron thick so four times as thick.

And the reason we chose the stick
interpose is because you wanted to put

forward X. in the interposer and
wanted to increase the robustness of the

interposer.

So the question is what is
the reliability so we've done.

In this show Maj a mess initial
characterization to see

how good is a contact with this tense
how many cut times can I remade to these

flexible interconnect and so
far I mean we don't see any

issues at all so the actually surprisingly
there are pretty robust structures.

We've done it using different structures
over there showed these using power mode

but you could also using some clever
prophecies make that a metal.

Yeah yeah.

Yeah yeah exactly so so
in the demonstrations we did we just.

For to exist as sort of demonstration.

It's a very interesting question because
we have actually a number of ideas that

relate to how you could do this but
ultimately in the real system if you're

going to have this as a permanent
structure it has to be out of metal and

we know how to do that.

You're right if you cannot use for
to resist permanently in the system

absolutely So
we have ideas of making that into a metal.

Yeah.

So you could dissolve it so we do so
right so we would actually just submitted

a paper where we're looking at using
these dissolvable on the structures and

so when I was saying you know.

Now we're proposing this as an idea
to help people do assembly when they

don't have flipped a book that's exactly
I was talking about use it to do assembly

to work the solar bonding once
you don't just put acetone and

get rid of it.

Centers.