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>> I'm really really happy to introduce today's speaker my colleague and I think I can say friend Matalon Swami Nathan. Who is just to give you a little bit introduction who is the where's my cheat sheet my cheat sheet is here on the back who is currently the John peepin chair in Microsystems packaging and electromagnetics in the school of Electrical and Computer Engineering here at Georgia Tech he has a joint appointment in the school of Materials Science and Engineering and since about 6 months he is the new director of the packaging Research Center here at Georgia Tech just a few works about about swamis credentials there is a very very long list he got his master's degree and Ph D. in 19899091 from Syracuse University went to I.B.M. off towards doing packaging for supercomputers is what I what I have kind of remember and then came to Georgia Tech in 994 so 25 years ago is that right.

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He has been involved that Georgia Tech in in number off center activities he was part of the E R C. That started the packaging Research Center back in the days he founded C 3 P S The Center for chip package and for CO design of chip package and systems those E's 3 P S and again now heavily involved in the packaging Research Center as the new director.

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He has more than 500 he and his students have more than 500 publications I read something like 20 plus best poster best paper awards that he has had with his students we are very very happy to have him here today and he will talk about the title it's going to be system scaling through heterogeneous integration Please join me in Val coming Swami my once woman a.

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Thank you. Thanks once again order for that nice introduction it's been pretty 5 years. Since I moved to Georgia Tech during those 25 years. 8 offices believe it or 8 offices with 81 being in the microelectronic the papered building basically that I moved into as of last week OK I'm still trying to open my boxes and digs like that.

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So anyway so it's a pleasure to be here and you know the title of this presentation a system scaling through heterogeneous integration I've been working the package Elyria know for 30 plus years or so and over the years I've seen various aspects of packaging and thanks to some of the efforts that we had at I.B.M. It led to those 1st Engineering Research Center Georgia Tech or the packaging Research Center and 25 years late to see still trying to say something about packaging and how important packaging this so what I'm going to do today is to try and paint a picture at a fairly holistic level on the importance of packaging as well as some of the technologies that.

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We're trying to develop at sea and before I get started I want our knowledge to many students we have 50 plus students now involved with the Center today around $25.00 faculty in walled lots and lots of staff and walled let me apologize so what I'm going to share with you today is not just my work but it's a it's a collective effort.

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So if you enter the petted building the minute you enter you'll see this figure or on the wall in that building and I think this is a very nice way of illustrating what system scaling is all about and so when I started at I.B.M. to Bill. These are very large machines and packaging was a very integral part of it and over the years as you can see the kind of computers that the fare able to build has not changed quite a bit and it's coming from 2 sources one is of course trying to scale the transistors and the 2nd is the packaging there's Well if you look at the kind of packaging that went into these large machines this was the C.P.U. alone required of $127.00 chips that had to be interconnected on a package with our own I would say $150.00 layers of wiring and so on and so forth and today if you look at a lot of the packaging that we use in some of the newer machines and some of the smaller machines that are shown over here the die mention of that package has come down quite a bit along with the size of the I.C.'s with lots and lots of wiring in it OK so if you look at system scaling and look at this figure it's clear that the systems of today are a whole lot smaller compared to the systems used to build around 25 years back and so if you look at scaling here OK size has decreased quite a bit so size in crude includes the war loom and the weight and so on and so forth the performance is improved many fold nobody can argue with that and the 3rd is the functionality of the the machines that we build today not only does it do computing it does many other things as well and hope is that sometime in the future you will have something that implanted Hopefully not but maybe implanted in the human body that does amazing things for you.

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So if you look at system scaling the question you need to ask yourself is how does one skill systems and at a very holistic level you can break up a system into 2 parts the transistors and everything but the transistors and if you look at the transistor you know there are nano scale so we know that we are down to the 7 on a meter technology today but if you take all of the high seas and all of the transistors in a system you'll find that it constitutes less than 20 percent of the wall of that system the remaining 80 to 90 percent comes from everything that's outside of that system and that's what we call us packaging and if you look at the Diamond sions of the components that we make use of on the packaging side it is much much larger than what you can do on the transistor side so when you ask yourself the question why are systems bulky have low performance costly under liable and so on and so forth it's not just about the transistors but goes way beyond that and that is the important message over here so transistor scaling alone is not sufficient for system scaling you need to work on package scaling as well killing of the package is as important as scaling of the transistors.

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So what exactly is packets. So let's take an icy and dicey has transistors in it and you build these transistors using different kinds of technologies it could be seen was different kinds of materials gallium arsenide silicon Germany and so on and so forth so when we talk about I.C. scaling the a basically taking these transistors and scaling those transistors to make them smaller and when you scan these transistors and make them smaller especially if you're trying to go after CMOS types of transistors they become much better in performance and so on and so forth so you get a large amount of benefit from it and this is what we call ours move slow but then if I have to build a system those transistors alone or modern nuff And that's where the package comes in so to get these transistors to work you need your power sources you need a battery.

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You need your thermal structures to be able to get the heat out because not all transistors are very efficient you need the board level technology to be able to connect all these ISIS together you need the cables and connectors to be able to interface with the outside world.

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And you have lots and lots of these passive elements these are there's a standard doctor's capacitors for guides meme's types of structures that you need to get this to work that's where the functionality comes in and of course today if you look at the cell phone industry the trend is not the words making the cell phones or the smartphone smaller but to make them extremely thin so therefore you are trying to Baghran the I C and to be able to embedded in the package so that you can make your systems thin and the way you make this happen is 2 different technologies just like what you do on the transistor side you can use organic laminate kinds of materials you could use materials for them silly couldn't last type materials you develop processes around it in such a way that you take all these components and try to many of them quite a bit so therefore if you're looking at system scaling you're trying to mean that many tries the transistors and miniature rising the package and what I mean by the package is all the components that you have including the wiring that goes outside of that I see to be able to connect all these terms of stars together.

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OK So that brings us to scaling trends now all of us a favor with more slow right and that's what is indicated by this line over here which says that the number of transistors doubles every 18 months on an I.C. and it's done amazing things for us in terms of the performance we've been able to get out of these transistors but then there is another metric that is very very important that is coming from the packaging side and that's what we call as the system component density it includes all of the inter contracts and every other structure that I showed you on the previous slide that allows you to build a system and on list the density that you have outside of the chip is the track with the density of transistors that you have within the I see it when you put the 2 together even though you have tiny transistors it's going to be too bulky systems OK so what we are trying to do or we would like to do is to find a way to reduce the IT terms of what we have been able to do on the I.C. side they say driven by most law and trying to sort of.

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Miniaturize these components outside of the I see that is driven by what we call as more than more small OK and the end goal is to read use this gap as much as possible so we want to make sure that tiny transistors are assembled onto tiny packages so that you can build your system.

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OK So that brings us to the concept of heterogeneous integration so heterogeneous integration neither is it only about the transistors or the devices or not is it only about the package OK but it's a combination of the 2 because you're trying to build a system that has it all different kinds of functionality embedded in them so think of a system where the system consists of very odd ones devices this could be the 3 D. memory devices the spintronic the compute logic and so on and so forth and you build I.C.'s with it the different kinds of technologies and then you are assembling get on to a package at a very very fine pitch such that the packet has functional layers in it that are lousy or too many miniature AIS the components that you need to support the art of functionality the optical and so on and so forth including your heat dissipation capability and together very able to do this well it can lead to these scaled systems.

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So. If you look at the industry today there is a trend all of a sudden towards heterogeneous integration and also if you saw the C.E.O. from GLOBALFOUNDRIES talk I think last semester or sometime during spring I believe. You would have heard this he was talking about heterogeneous integration as well the question is why why would a company like Global Foundries be talking about heterogeneous integration and part of the reason why is because as you begin to do things more and more more literally on a single I see that DI cost begins to go up exponentially as you begin to scale the mentions of the size of those transistors beyond the $10.00 anime to it so there is a sweet spot in terms of what you want to accomplish in terms of the die area and the DI cost when you do the scaling but then you still have to build a system and then stuff trying to go after the smaller take integration that can be very very expensive there is a trend towards what we call us holistic integration where you take multiple chips you take an ethic you partition it into smaller chips that we call a chip let's and you connect them all together using very very high density wiring on a packaging platform that is shown over here and this.

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This line came actually from DARPA they are saying that the shift to packaging is important because that's the most cost effective part towards the further system scaling. So with that as a background let me get a little bit deeper into it and I'm going to start looking at different kinds of applications where we believe packaging can play a very very important role and some of the research that we're working on and all of the 330 is competent of research so let's take this example of flying these intelligent drones the hope is that someday you have these drones if you look at.

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The news from Amazon they're talking about having these drones flying everywhere dropping packages for you so the hope is that these are intelligent drones that can fly themselves can navigate by them see themselves so how is it being done so this is one example with a colleague of mine Professor Jeffrey Choudary who is working on artificial intelligence.

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Drones and so on and so forth so when you build these kinds of Braun's there are 2 parts to it one is you're trying to fly this drone in and while I am and that is well known right so you're trying to have the drone learn in terms of what is going on around there why meant and then that is the 2nd part where you're trying to fly this drone in an environment that you really don't know much about and it's learning in the process OK so there is one part where you're pre-print in the drone and the 2nd part is drawn is making use of that information to be able to learn as it begins to navigate through.

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This hallway that a short a way here so if you take this you break this up into what actually goes inside of the drone it looks in this form so there is some kind of a camera there that is taking pictures so it knows exactly what that moment looks like and then there's a lot of memory so they have the data then the S.T.T. Rams and so on and so forth along with.

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Logic and you're trying to implement this intelligence in 2 forms one is through these convolutional mutant networks and the idea here is that you want to be able to reduce the amount of communication that you have between the neurons and therefore you try to. Make things very fast and the 2nd part is through plans for learning so now you're trying to make use of the information that you want to be learned in a new environment you're transferring part of that knowledge to be able to learn what is going on in the environment to understand how open that it so if you take this problem and break it up into the hardware science of things what you want to do is to do very fast computations in a real unknown environment and what that translates to for us who design packages and so on and so forth is very lowly in C. interconnections you want to be able to communicate between the logic chip and the memory chip at very very high speeds and the 2nd part is you want to make sure that these rules don't begin to fall from the sky because of lack of power and it turns out that when you look at these computations 70 percent of the power is consumed by computing it doesn't come from the motors that go into that drawn that actually comes from computing and the only VERY by which you can conserve your battery is by making sure that you have the very low energy bit connections of communication.

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And you also want to make sure that you have these very high reliability connections that you can establish in this kind of. Of our of our hardware. OK So let's look at the system architecture itself so if you go one layer down what you have are a bunch of chips that are connected to each other and depending on the kind of neural network that you're trying to implement the connectivity between the chips is going to be very different OK so that's why when you look at E.I. types of applications it's the application that determines what the architecture is going to look like not the other way at all most of the time we build 3 use it and build an application around it with a lot of these kinds of applications you're doing exactly the reverse so in this particular example you have a bunch of chips that are connected to each other through very dense interconnections and what you want to do is if you look at the connectivity it's across the edge OK so it's an edge to edge connection between the chips and you're going after these massively powerful architecture and your goal is to be able to transport this these bits at a very very high speed between these chips getting you up to maybe out on 16 gigabytes per 2nd.

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But you're trying to do that there are certain sort of metrics you need to worry about and given those performance metrics the question is how do you want to sort of achieve them. The 1st metric is you want to have a very high aggregate data rate between the chips going beyond let's say one terabyte a 2nd and what that translates to in terms of these wiring structures that you see over here is that you need very very high density wiring along with a very fine assembly pitch and you type to assemble the chip on to that substrate The 2nd is what I'd mentioned earlier you need very low energy put a bit going down 2 point one Pico dual sport bit of soul and the way you do that is by making these lengths of these interconnections extremely sharp and making sure that the capacitance associated with it is very very small as well and that's part of the reason why you literally want a brick wall these chips are right next to each other and run these wires from one chip to the other and the 3rd is the lower bit terrorist in this translates to the reliability of the system you want to make sure that there are no errors so that you have a bunch of bits that you are transmitting you want to make sure that you never get into a scenario where a bit one gets affected notices a bit 0 or vice versa so the big hurdle rate is a very important metric off that and this is where the POS talk that you have between these interconnects along with the power delivery schemes that you actually make use of comment comes into play so how do you make this happen and there are only 2 ways to do it one is what we call a 3 D. integration for 3 D. integration is you begin to stock chips on top of each other so you reduce that interconnection lent to the communication there are companies like D.S.M. C..

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You know companies like Intel and others who have started releasing products one of the challenges that you have in 3 D. integration is that it's very hard to go beyond 2 chips in terms of your ability to want these chips together and connect them to each other and that is always an issue related to power delivery and the management.

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And the 2nd way to do it is what we call as to Harvey integration those are the lateral connections that you have from chip to chip the surely you need bought moving forward because a lot of the memory structures we're going to have is going to be 3 D. treaty stacking of I.C.'s and then you have the logic that's going to be separated and you want to connect them want together to this 2 and a half cradle for.

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Solution So how do you go about doing it now if you look at the landscape in the area there are several solutions being proposed right I'm not going to go to every one of them the one that appears to be mainstream today is to use a piece of silicon to do the interconnection between the chips we call that as the silicon interposer kind of a solution and you have companies like the A 7 C. we have a process around it so you can tape out your chips deport your package and then build it for you and what I'm going to do is to talk about a different technology that we believe gives us some opportunities that you can never get out advantages you can never get with the silicon interposer technology and that's what we call as the last interposer technology OK So once again this is all.

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COM put it over ongoing research and the idea here is to do something new that nobody else is looking at such that we can achieve things much more than what some of the present technologies are able to support so the idea is the following you take a piece of glass OK this is tinted glass and the diamond chin of the glass itself can be either small or large and you these kinds of glass substrates come in different thicknesses Let's take an example here you're taking a 300 micron think Glass substrate so let's say that and if you take a glass substrate it said insulating material unlike some it conducting material like silicon right so therefore it gives you some nice properties as you get into higher frequencies then later so that you drill holes through it let's head to Ali's right and you fill those holes you metalized and then you begin to Larman it right polymer layers on either side and metal eyes the top and bottom layers of the substrate to create your interconnections on them we call these as the redistribution is what are deals and then you assemble the I.C.'s on top of a very fine pitch going down to maybe 10 microns or less in terms of pitch and on the other side you would take this and mount it on a printed like right now the argument I'm going to make is a structure like this even though it has many challenges that one needs to work come to get it to work and gives you some opportunities that you will never be able to get with most of the technologies especially when you're trying to get into very very high density one OK The question is why so P.R.C. has been working on this for 5 to 6 years or so so why is this so unique so.

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So let's look at the ad. One teacher's So one of the nice things with glass in the poses is that it comes on very large panel sizes and these are Squier panels not circular unless the silicon wafer is a squired paddles and therefore with this large substrate sizes so large panel sizes depending on the size of the substrate you can argue that you can build many of these all in particle you dice them up and therefore the cost of a single substrate can actually be low.

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The 2nd is that you are not limited in terms of the aspect ratio for the interconnect that you actually build. And think called structures the very tall structures that are allows you to reduce the resistance of these interconnects quite a bed so that you are able to transport these bits at a very very high speed the target is that you can do a direct attach of copper slots to the I.C. Now if you look at an application like a smartphone application where the thickness is very very important then you have to take an I.C. you have to thin it and you have to embedded I see and you won't do NOT want to introduce any parasitics by assembling this I.C. onto the substrate Instead you want to be seamless interconnection that a short over here we call it as found on panel of packages but on the other side you want to access to the back side of that I see that you can get the heat out.

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And you have an opportunity when you work with these kinds of materials to expose the backside of the I C and I patch a copper slug but the key to it so that you can get the heat out. Number 4 is the C.P.U. of the material itself if you look at these glass substrate materials what is shown over here along with these MIT polypill materials that you have on either side you can build a structure such that you can paler the C.P.O. of that material in such a way that you can eliminate one level of packaging and I'm going to come to that the wrong.

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And you can also work with ultra thin glass substrates OK So this is an example here from chart where they are able to take a 30 micron thick glass substrate and basically bend it a longer using axial direction without actually breaking so you can now take very thin glass substrate laminate them on top of each other basically using an adhesive build a structure multi-layered structure that has some very very interesting properties with it and of course this is from Corning where you can you work with very very large paddles and get into those who hold to the old man of that and if you like and finally the reliability remember that this package is in between the chip and the board so you want to make sure that on one side you are able to get higher than a liability as far as the chip goes and on the other side they want to get very high reliability as far as the board goes that's what because the fatigue life OK so you don't want these connections to break and by tailoring the C P off that substrate you basically can ensure that you can match or at least improve the fatigue life on the chip side as well as the board side so that you can improve the overall viability of the structure.

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So this is what it would look like so this is what I was mentioning and most of the time when we try to use silicon interposer kind of a solution notice that there's another package that you need over here that are gonna package acts like a buffer OK that are allows you to match the C.P. that you have on the side with the C T mismatch that you have on them on the side so most of these silicon interposer kinds of solutions will have an extra layer of packaging that you can eliminate by using this glass and deposit.

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So we know P.R.C. has been working on this for quite some time these are some examples that I'm going or flash through that are several processes that we have been developing working with different kinds of materials low stress materials located low DK low D.S.P. T.V. those double up in the process and we are able to do lines and spaces of the order of 2 microns line with and 2 micron lines bases very similar to what the silicon interposer technology is able to do we're also able to build these micro vias so the dimensions of the vias that you have when you look at these are Deal liers is down to our own you know a few microns of so.

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Around 4 and a half to 5 microns or so and we're also trying to develop of a bit you can assemble these chips at very very very fine pitch onto the substrate using new concepts based on those nano porous copper for them centering that gets us down to pictures of the order of 20 of my conscious.

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So what does this actually buy you OK So let's go back to the metrics that I mentioned right and what you have on the X. axis is the channel end and the Y. axis on the left hand side represents your maximum data rate and the right hand side vertical that you see is the energy and people will support it because you have reduced the length of the connections.

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And because you are able to use dielectric materials that have a very low dielectric constant associated with it you'll find that for any given channel length the amount of energy that you can zoom for transmitting each bit as well as the data rate you're able to achieve is roughly 2 times better than what we are able to do with the silicon interposes OK and one can argue that that is not good enough and what this kind of for technology buys you is that if you look at a lot of the Artificial Intelligence intelligence types of applications the size of the substrate is beginning to grow not really deals and the reason is because you want that interposer to look like your printed circuit board so you want to sort of park as many components as you want and as the size of the substrate actually increases and you begin to get this kind of performance you start getting a lot of more advantages as well you know relation to that when you begin to optimize the aspect ratio you'll find that you can get to very very high data rates along with very high signal density signal densities of the order of 4 on $330.00 signal lines per minute meter read the data rate of your copper on 15 to give it a 2nd and if you look at the total through put you're able to get there stimulation is that it's going to be off your profit on each terabytes or 2nd or so and all we have done over here is to play and optimize the aspect ratio of these interconnect to be able to get.

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So let me switch gears a little bit and get into another application. I think that is most applicable for many of us and that's that there is a day of data centers in energy so if you look at all these data centers. That that the Googles of the world actually build there is a power source that that is poverty up all these data centers and if you look at that power source it comes from the AC side comes from the power grid but I couldn't tell you are taking that AC source and you're kind of working it into D.C. and then you're down converting it to a World page that you can then use to switch these transistors so the transistors Spicher toward age of let's say one ward and each block that you see it represents the down conversion from one voltage level to the next and if you look at the numbers within each one of these blocks that represents the power efficiency so it basically means a high in the high value of partition see over here means that the total power of the output is very close to the power of the input any difference that represents the very stage an energy so if you go through these blocks and go to the very last 2 blocks over here you're down to 85 person and 65 person efficiency if you take the product of the 2 you're at 55 percent what that means is that for every 2 watts of power that you draw from the public that one water is being wasted OK and that's.

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Creating a huge amount of heat and the bottom side of this bottom line is if you have a V. by which you can improve the efficiency let's say by 20 percent in the last 2 blots it better keep translates to a 20 percent reduction in energy consumption. So how do you do that OK the there you do this is by trying to bring your power source close to the chip that is actually drawing the power right so therefore you want to take that back to what we call as the point of load convert or move it closer and closer to the chip and by doing that you're reducing all of the losses due to the shorter current parts and therefore your bump up they feature it's easier said than done because to make this happen you need very high switching speeds for these kinds of converters which requires new device technologies so you cannot do work with silicon you have to go to gallium nitride technology and you also need very high power efficiency which means that all of the passive components that you that you need outside of the I see should have very very low loss the loss of subsisted.

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So that comes to the power delivery scheme and one can argue that if you're trying to go after the true genius kind of a concept integration kind of a concept but you're working with multiple I think is fair let's say one of the races that you're trying to integrate in the package is a buck converter right that is in very close proximity to that I see then you get some very significant advantages and one is the politicians.

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And the 2nd is the fact that it's very clause means that all of the cards going through very short distances on those interconnect and therefore you're using the mosses even more so we call this as an integrated regulator and to make something like this happen you need these inductors that are embedded in the package right outside of that I.C..

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So how do you do that a very important metric is the amount of current density you can support for these kinds of integrated more day to day glitters want to get to our own 10 AM spot millimeter squad or so and at the same time we want to reduce your parasitics as much as possible to ensure that you keep your losses small and that's where the more you will take Miss comes in.

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Right as well as the interconnect lead comes in and the only way to do this is to replace all these discrete components that you have with tin from components that are embedded into the layers of the package and that's what is indicated over here and this is some work that we did a few years back and the idea here is to build these inductors that are integrated along with the converter on a single package and if you look at these are in this kind of model here you do not have to work with very advanced technology Nords for your buck converter unlike what one needs to do if you're trying to integrate that back and work into that and so see which is what the short on the 2nd column so you don't have to work with a 22 nanometer technology for the buck converter Instead you work with the 139 a meter technology embedded inductors in the package switcher but converters at a very high frequency of the order of 100 megahertz and get efficiency numbers that are very close to.

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S.O.C. type of a solution so by the way the 2nd column is what Intel has demonstrated a few years back. So if you look at a lot of the future power delivery solutions you want to take the last 2 blocks that I showed you for those data centers combine them together OK and that's what we call as a single stage 48 to one world power conversion and that requires new device technology for example gallium nitride technology and this is what we're working on OK So you want to be able to switch these devices that are on 10 megahertz or so and if you look at the figure of merit you know as human we are able to do this right you'll get tremendous improvements in part of the as well as figure of merit you're able to achieve a solution like this.

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So this is what we're working on so think all of these gallium nitride devices that doesn't. Have to be. It includes as well assembled at a very very fine pitch on to a substrate of a package where you have embedded capacitors and embedded magnetic clears and you could have the S.O.C. on the same package as well but in this embodiment over here you have 48 wards goes in and one wall comes out right at very very high current of the order from 200 amps so this is some work we have been working on on magnetic materials and this is a very very difficult problem because you know when you work with these magnetic materials depending on how you synthesize these materials you're always limited in terms of the maximum or the value of permeable it or you can achieve and at the same time the magnetic last time that you're able to achieve and most of these materials as you go higher up in frequency the moderate opposition completely goes away and you're left with a very very lossy material OK So synthesis of these materials are very very important and I've been working on trying to work with these magnetic sheets as a way to integrate these inductors and that is what a shown over here so this is some work that we are trying to do to be able to get very high inductance densities OK at very very low loss by trying to reduce the magnetic loss standard as much as possible and building the toroidal inductors that you can embed inside of that inside of the package.

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And the next area is in the area of embedded capacitors this also is very important because with all these point of load converters at the OUT port you have a low pass filter circuit you have a series inductor that is generating the current for you and then there is a shunt capacitor that is pulling the wool to ripple so that capacitor is as important as that inductor that generates the current and unless you're able to embed these capacitors and ensure that it has very very little parasitics you're not going to be able to manage the wall to triple or are these kinds of converters so this is some work that we've been doing recently the facts.

[00:40:17]
Grand spurning just graduated he does definitive pieces his spot of the material science department and so what he's been working on is to try and create these capacitors using tantalum oxide dielectrics into the part of electric material that gets you some very interesting properties in terms of the capacitance density that one can achieve with this and if you look at the process itself we try to build it separately and then it's a plan for process so we transfer the filum onto the substrate that we're actually trying to build and water Grant has been able to sure is that he's been able to keep the extremely low at our own one megahertz but with a capacitance density of around one microphone and it will mean this was very hard to do at the package level because of the open oddity of the package layers itself but this is something that we've been able to accomplish with and see that's considered to be state of the art because if you compared with everything else that is available as discrete components this compares favorably.

[00:41:26]
Than another area of the application is in the area of communication and all of those are favor with 5 G. and what it does but there's also another frequency band that is emerging in the area of SUP that hurts communication and if you look at a lot of the applications here it's in the area of my more communications imaging nondestructive testing and so on and so forth but the frequency range that is being targeted it's between on point $12.00 on one.

[00:41:55]
Question is if these are the some of the emerging applications. What are the packaging technologies that you need to develop and one example is surely here so if you look at the transmitter modules for a sub better Hertz communication kind of a vehicle the Almonte of heat that you're going to gender it is between $5.00 to $10.00 times higher than what you have for a fight the application and part of the reason is because if you look at these part amplifier chips that are going to be built using these $35.00 materials there their efficiency tends to be very low the best efficiency you're going to get is of the order of 4 and 25 percent which means 75 percent of that power gets converted to heat so you have to be able to get the heat out and the only way to do that is through the back side of the chip so think of a glass interposer or glass substrate which is extremely thin as thick as the thickness of the chip itself you are creating cavities in it and these are the 2 cavities you embedded that Dian it right ensuring that there is no dice shift and then you're trying to remove the heat from the back side using that see a vapor chamber that is embedded in a cavity in the printed circuit board OK So this is ongoing work but you get a feel for some of the technologies we need to double up moving forward to be able to support a lot of these applications so building carroty is becomes extremely critical and this is some of the latest results that we have in our ability to build very high position cavities and if you look at the substrate over here on the back side you actually see this sheet of glass laminated on it it's transparent you don't see it you can also H. it out so you can remove the spot so you don't have a through cavity or you have a blank cavity and you can embed dies in it with very minimal dye shift of your profile on to my colleagues so you can build extremely thin models with.

[00:44:00]
And this is our grand vision and grand goal to be able to build a more do you like this stack these models on top of each other that along with an tenors so that you can do your scanning both along the E.P.A. and at a frequency of our own $140.00 that it's the.

[00:44:20]
Right. And fire and involved yet is that overall integrated into this class street so with the remaining time that I have to the few minutes a let me just get into the very last topic and then I'll stop there so I had to be build these systems and as we begin to design these and develop new technologies the complex that the of these systems is increasing many for it's getting to a point where it's becoming impossible to actually design is OK So the question is can machines help design these systems and more importantly if you're trying to design such complex systems you get into the issue of design response right because you're making mistakes and you're responding that you get it right and that's a terrible way of doing X. OK Can machines help do that the 2nd is the reliability you how bored the heart and the functional letters can one improve the reliability of these machines at the design phase and can the machines begin to predict failures of these and also can machines help determine new packages and system architectures right So overall what we want to do or what what are thinking this is to start looking towards machines to improve human predicted productivity by orders of magnitude so what we have started doing within the C. is to.

[00:45:53]
Create a machine learning environment that allows us to work on different types of designs working where different kinds of materials and different kinds of processes are the hope the designs that we actually keep out our extreme the robust and makes full use of the processes and the materials that the make use of it so I'm going to talk very briefly about one aspect of it and that's in the area of design optimize ation all of us are familiar with this issue right you're trying to design let's say a chip system and there are lots of parameters you need to tune right and you begin to tune them and then you realize that it's taking forever.

[00:46:36]
You take shortcuts and you decide that out of 100 but I mean does only 2 are important you focus on these and in the process you make the sticks and as a result you have the design response so the question we asked ourselves is can we make use of machine learning as part of this kind of an environment to be able to ensure that we don't make those mistakes so that we can end up with an optimized design.

[00:47:02]
So what is the issue over here so if you look at the general area of optimize zation when you're trying to optimize the design and if you're looking at an arrest point surface like this that is of the converts type you'll find that almost any optimisation technique that you make use of will always can words those global minimum that are surely very easy right but in reality when we work with designs and different kinds of materials and processes etc You're working with the response of as the extremely complex OK And in the midst of all this you're working with lots and lots of but I mean there's that you need to do you want to be able to get to the optimal design and this is what requires a hard compute problem and if you look at a lot of the people both on the hardware on this and the software side they're trying to tackle this issue by coming up with new devices new interconnection technologies as well as new software techniques so what we have been doing is developing techniques specifically for packaging that allows us to come up with very very robust designs and I'm just going to focus one of these over here and show you the results today OK So those are high speed channel so you are connecting chips to each other but running bits at a very very high speed and you want to optimize the system such that you get a better best performance possible and if you look at the simple example over here there are only 6 parameters that you need to tune and if you look at all possible combinations it takes forever to do this right so you don't want to be able to do this manually so by using these machine learning techniques to get able to make predictions in terms of what the performance of interconnect channel is going to look like and if you look at this survey machine learning is very good at making predictions but when you look at the.

[00:49:01]
End of problem we're trying to solve which is an optimize the problem with making use of stochastic techniques to be able to solve the problem so when you're making you making use of these statistical techniques there's always a certain level of uncertainty associated with how good your prediction is so therefore what you want to do is that along with the predictions that you're making you're also trying to provide an uncertainty around it indicating how good is your prediction so that in case you feel that the prediction is not good enough you can always add more training data to it and all of that is done automatically adaptively without 0 human intervention so this is work that's going on so the validation cases that you see over here represents predictions so there are 2 lines on top of the 3rd one is actual the the 2nd is predicted and if you look at the predicted one along with that you have the shaded area that represents what we call us uncertainty bounds that tells you that this is the prediction that we're making but there is an upper limit and a lower limit in terms of confidence because that gives you a wealth of information in terms of how reliable the system is actually going to be.

[00:50:14]
And we've just started working on this and this is really the very last slide the technical part and what it basically says is that if I have a bunch of materials available to me a bunch of technologies available to me why do I need a human to determine which combination of technologies is going to give me the best solution why not make use of machines.

[00:50:40]
And this is a project that we just got started and I made the statement over here just to get all of you motivated we can begin to you see a lot of these machines are machine learning based and go out of them's to do a lot of the designs and the predictions for that So with that I'm going to conclude so one of recognize all of the the students the faculty the staff or part of the center there are many of them as you can see the also collaborate with and the faculty come from 44 different schools.

[00:51:17]
We also collaborate with many. Companies as well as government. Organizations and what we are trying to go off to is what we call of the medicine on packaging OK Not only do we want to be focused on the packaging side but we also want to make sure that the package enables what happens on the silicon side the chip side as well as on the systems side OK And the idea here is you connect the dots you'll always be able to come up with the smallest system possible and that's what we call a system scaling right so these are our current collaborators 30 more than 35 of them and we also have these shared use of the facilities that are all part of I.E. in today for all of you to use so that I just want to summarize saying that when you talk about system scaling Please do not but if you look at only transistor scaling it goes beyond that it includes back it's getting this bill so with that I'm going to stop right here and if you have any questions and be very very happy don't.

[00:52:31]
You know. Force. Please. Dielectric material but the dielectric material saw the silicon interposer if you look at a typical Can of the line process like for example the A Since he does. Dielectric material is fixed. OK so here we have the flexibility of using other materials as well so the reason why there is a difference in data that comes directly from the capacitance of those independents because the resistance is the same it's the same dimensions for the interconnect it all comes from the dielectric constant of that material which is very low for the polymer materials that the Americans off.

[00:53:31]
Yes So this was based on a better rate of 10 to the minus 12. Right. Yeah. Yes no. Very good point right so if you take a silicon interposer just think about it what would you do write your paper out of design. They would build it for you.

[00:54:02]
You're not there yet that glass right there is a supply chain that needs to come together that has to be an infrastructure that has to come together so today if you look at a lot of the glass interposer kinds of solutions that are being built you don't you cannot build it all at a single place a single factory it has to go to multiple places so multiple teams then companies have to come together to be able to deliver a product like this and so that's going to take time so it's not a costly to the issue but more often infrastructure than the supply chain related issue and that takes time.

[00:54:35]
And typically if you look at packaging right to go all the way from concept to manufacturing takes it on 10 years it takes time for example if you take a device based technology it takes 25 years for a new technology to go from concept to actual manufacturing so it takes time and I believe that over time that's going to happen but it hasn't happened yet and that's why it's all pretty competent of the search at this point.

[00:55:24]
Yeah so there is a lot of in terms of infrastructure that's quite a bit facilities not generally as part of P C but as part of this well OK so. If you look at P R C A lot of the assembly level technologies that we have is Chip the substrate so you take a substate your symbol the chip onto it developing new technologies in that area as well there's also some work going on in the area of die today for level bonding OK some of it is happening here at Georgia Tech some outside and did odd some facilities in that 80 year olds.

[00:56:12]
Yes Yes they're all related and in fact a lot depends on the size of the cavities the number of cavities the number of truly as you have the it all sort of into the needed and the fracture toughness is a big issue for us in terms of how you actually construct the structure itself.

[00:56:32]
You know before the build up later this. Year. Thank you.